Method of forming an electrostatic discharge protection circuit

A process of making a circuit for triggering an electrostatic discharge protection circuit comprising the steps of:

• forming bipolar junction transistor in a semiconductor substrate, said bipolar junction transistor including an emitter, a base and a collector coupling said emitter to a bond pad;
• forming a plurality of field effect transistors in parallel, each said field effect transistors comprising a first source/drain region and a second source/drain region;
• and
• resistively coupling said first source/drain region of each said parallel field effect transistors to said base, such that said parallel field effect transistors trigger said bipolar junction transistor upon an electrostatic discharge event.

A method of forming a semiconductor device comprising the steps of:

• providing a semiconductor substrate of a first conductivity type;
• forming a tank region of a second conductivity type within said substrate;
• forming a first doped region of said second conductivity type within said tank region;
• forming a second doped region of said first conductivity type within said tank region adjacent said first doped region;
• forming a third doped region of said second conductivity type within said tank region spaced from said second doped region;
• forming a field effect transistor within said substrate spaced from said tank region, said field effect transistor comprising first and second source/drain regions of said second conductivity type spaced by a channel region;
• and
• resistively coupling said first source/drain region to said third doped region.

A method of forming an electrostatic discharge protection circuit comprising the steps of:

• forming a doped tank region of a first conductivity type in a silicon substrate of a second conductivity type;
• forming a plurality of n doped and p doped regions within said substrate, said plurality of doped regions including a plurality of first source/drain regions and a plurality of second source/drain regions separated by a associated channel regions wherein each of said source/drain region sis doped to said first conductivity type and is spaced from said tank region, said plurality of doped regions also including at least one heavily doped region of said second conductivity type formed within said tank region;
• forming a plurality of doped resistor regions, one each of said doped resistor regions coupling an associated one of said first source/drain regions to said heavily doped region;
• forming a polysilicon gate over each said channel regions and insulated therefrom;
• diffusing said plurality of n doped and p doped regions;
• and
• depositing and patterning at least one metal layer to form a bond pad coupled to said heavily doped region and to couple said second source/drain regions and said gate to a supply voltage node.