Method of making floating gate junction field effect transistor image sensor elements

A method for fabricating a floating gate junction field effect transistor sensing element at a face of a semiconductor substrate, comprising the steps of:

• forming a drain region of a first conductivity type in the semiconductor substrate of a second conductivity type;
• forming a source region of a first conductivity type in the semiconductor substrate spaced from the drain region;
• forming a gate region of a second conductivity type between the drain region and the source region, said gate region operable to form a potential barrier in the gate region at a substantial depth from the face for collecting carriers of the second conductivity type formed responsive to incident light, said barrier acting as a probing current well for a current of a first conductivity type;
• forming a capacitor for coupling to the gate region, the capacitor operable to apply a pulse to the gate region for sweeping out the carriers;
• and
• forming a capacitor insulator layer on the gate region;
• forming a capacitor conductor on the capacitor insulator layer over a portion of the gate region;
• and
• connecting the capacitor conductor to a pulse source for supplying the predetermined pulse.

A method for fabricating a floating gate junction field effect transistor sensing element at a face of a semiconductor substrate, comprising the steps of:

• forming a drain region of a first conductivity type in the semiconductor substrate of a second conductivity type;
• forming a source region of a first conductivity type in the semiconductor substrate spaced from the drain region;
• forming a gate region of a second conductivity type between the drain region and the source region, said gate region operable to form a potential barrier in the gate region at a substantial depth from the face for collecting carriers of the second conductivity type formed responsive to incident light, said barrier acting as a probing current well for a current of a first conductivity type;
• forming a capacitor for coupling to the gate region, the capacitor operable to apply a pulse to the gate region for sweeping out the carriers;
• forming a channel of the first conductivity type in the gate region;
• implanting the channel with phosphorus at a concentration of 1.0 to 3.0.times.10.sup.12 ions/cm.sup.2 and an implantation energy selected from the range of 50 to 200 KeV;
• and
• driving the implanted ions into the gate region at a temperature of about 1050.degree. C. for about 24 hours.

A method for fabricating a floating gate junction field effect transistor sensing element at a face of a semiconductor substrate, comprising the steps of:

• forming a drain region of a first conductivity type in the semiconductor substrate of a second conductivity type;
• forming a source region of a first conductivity type in the semiconductor substrate spaced from the drain region;
• forming a gate region of a second conductivity type between the drain region and the source region, said gate region operable to form a potential barrier in the gate region at a substantial depth from the face for collecting carriers of the second conductivity type formed responsive to incident light, said barrier acting as a probing current well for a current of a first conductivity type;
• forming a capacitor for coupling to the gate region, the capacitor operable to apply a pulse to the gate region for sweeping out the carriers;
• and
• forming the drain region in an endless structure laterally enclosing the gate region and the source region, such that the drain region acts as an electrical boundary between the element and the gate regions of like adjacent elements.

A method for forming a floating gate junction field effect transistor image sensor array at a face of a semiconductor substrate, comprising the steps of:

• forming a plurality of generally annular electrically interconnected drain regions of a first conductivity type in the semiconductor substrate of a second conductivity type to define a plurality of sensing elements arranged in row and columns, the drain regions separating each element from adjacent elements;
• forming in the semiconductor substrate for each element a gate region adjacent, and laterally enclosed by, a respective drain region, each said gate region operable to form a potential barrier for collecting carriers of a second conductivity type formed responsive to incident light, said barrier acting as a probing current well for a probing current of the first conductivity type;
• forming for each element a source region of the first conductivity type laterally adjacent and enclosed by a respective gate region and spaced from a respective drain region;
• forming a capacitor insulator layer over each gate region;
• forming for each row of elements a continuous capacitor conductor layer on the capacitor insulator layer so as to cover a portion of each gate region in the row, such that a pulse applied to said capacitor conductor layer will be operable to sweep out the carriers collected by the potential barriers of the row;
• and
• forming a continuous second conductor for each column of elements to connect source regions of each element in a respective column to a sense node for sensing a change in the threshold voltage of a selected gate region responsive to the collected carriers.