US 5,290,718 A · Simplified high reliability gate oxide process

Abstract

A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors. The invention proceeds by stripping the EPIOX layer over the CMOS transistor active areas without growing a sacrificial oxide SACOX layer, and then removing the photoresist CMOS active strip mask. This step is followed by growing a gate oxide layer over the CMOS transistor active areas using a wet oxide grow process at relatively lower temperature than a dry oxide grow process. Other steps of the invention include forming the combined thicknesses of the CVDSIN and EPIOX layers to provide the control screen necessary for controlling the subsequent base implant to maintain the desired .beta. specification for bipolar transistors. The layers are formed in a thickness ratio CVDSIN/EPIOX in the range of approximately 5/3 or smaller to achieve the desired reduction in silicon defects and increase in current leakage test yield.

Claims21

Dependent claims

A wafer fabrication process comprising CMOS fabrication steps for fabricating CMOS transistors in a substrate of semiconductor material including an NWELL definition mask, etch, and N type dopant material introduction sequence forming an NWELL in the substrate, a PWELL definition mask etch and P type dopant material introduction sequence forming a PWELL in the substrate, growing an epitaxial layer (EPI) of semiconductor material over the substrate, growing an epitaxial oxide layer (EPIOX) over the EPI layer, depositing by chemical vapor deposition (CVD) a nitride layer CVDSIN over the EPIOX layer, and a CMOS transistor active area definition mask, etch, and field oxide (FOX) grow sequence for framing CMOS transistor active areas of the EPI layer in FOX, an improved CMOS active strip mask, etch, V.sub.T adjust and gate oxide grow sequence comprising:

forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer;
introducing P type dopant material through the EPIOX layer into the CMOS transistor active areas with the photoresist active strip mask in place for adjusting the threshold voltage (V.sub.T) of the CMOS transistors;
stripping the EPIOX layer over the CMOS transistor active areas without growing a sacrificial oxide SACOX layer and then removing the photoresist CMOS active strip mask;
and growing a gate oxide (GOX) layer over the CMOS transistor active areas using a wet oxide grow process at relatively lower temperature than a dry oxide grow process, said wet oxide grow process being at a temperature no greater than approximately 850.degree. C. followed by anneal ramping of temperature to a relatively high temperature and return to a relatively low temperature in a rapid thermal cycle.

1 more element

A wafer fabrication process comprising CMOS fabrication steps for fabricating CMOS transistors and bipolar fabrication steps for fabricating bipolar transistors in a substrate of semiconductor material including growing an epitaxial layer (EPI) of semiconductor material over the substrate, growing an epitaxial oxide layer (EPIOX) over the EPI layer, depositing by chemical vapor deposition a (CVD) nitride layer CVDSIN over the EPIOX layer, a CMOS transistor active area definition mask, etch, and field oxide (FOX) grow sequence for framing CMOS transistor active areas of the EPI layer in FOX, a base definition mask, etch and P type dopant material introduction sequence forming the base of bipolar transistors through the nitride layer CVDSIN, an improved CMOS active strip mask, etch, V.sub.T adjust and gate oxide grow sequence comprising:

etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer;
introducing dopant material through the EPIOX layer into the CMOS transistor active areas for adjusting the threshold voltage (V.sub.T) of the CMOS transistors;
stripping the EPIOX layer over the CMOS transistor active areas without growing a sacrificial oxide SACOX layer;
growing a gate oxide (GOX) layer over the CMOS transistor active areas using a wet oxide grow process at relatively lower temperature than a dry oxide grow process;
a base definition mask, etch and P type dopant material introduction sequence forming the base of bipolar transistors through the nitride layer CVDSIN;
forming the combined thickness of the nitride layer CVDSIN and epitaxial oxide layer EPIOX to provide a control screen for controlling the base implant to maintain a desired .beta. specification for bipolar transistors;
and forming the respective layers in a thickness ratio CVDSIN/EPIOX in the range of approximately 5/3 or smaller.

4 more elements

A wafer fabrication process comprising BICMOS fabrication steps for fabricating CMOS transistors and bipolar transistors in a substrate of semiconductor material including an NWELL definition mask, etch, and N type dopant material introduction sequence forming an NWELL in the substrate, a PWELL definition mask etch and P type dopant material introduction sequence forming a PWELL in the substrate, growing an epitaxial layer (EPI) of semiconductor material over the substrate, growing an epitaxial oxide layer (EPIOX) over the EPI layer, depositing by chemical vapor deposition a (CVD) nitride layer CVDSIN over the EPIOX layer, a CMOS transistor active area definition mask, etch, field oxide (FOX) grow sequence for framing CMOS transistor active areas of the EPI layer in FOX, CMOS active strip mask, etch, V.sub.T adjust and gate oxide grow sequence, a polygate definition mask and etch sequence, a base definition mask, etch and P type dopant introduction sequence implanting the base of bipolar transistors through the nitride layer CVDSIN and EPIOX layer, and an emitter definition mask, etch and N type dopant introduction sequence followed by an emitter anneal step at relatively high temperature, subsequent to the CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence, the improved steps for reducing stress defects in the EPI layer comprising:

forming the combined thickness of the nitride layer CVDSIN and epitaxial oxide layer EPIOX to provide a control screen for controlling the base implant to maintain a desired .beta. specification for bipolar transistors;
forming the respective layers in a thickness ratio CVDSIN/EPIOX in the range of approximately 5/3 or smaller;
forming a protective nitrox layer over the CVDSIN layer during the FOX grow sequence;
preserving the protective nitrox layer during the CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence;
and exposing the protective nitrox layer over the nitride layer CVDSIN during the polygate definition mask and etch sequence for protecting the nitride layer CVDSIN during a poly etch.

2 more elements

Dependencies are inferred from the claim text.

Simplified high reliability gate oxide process

Life of this patent

Simplified high reliability gate oxide process

Life of this patent

Abstract

Claims21