A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first buried layer of a first conductivity type, a second buried layer of a second conductivity type and a third buried layer of said first conductivity type on a surface of a semiconductor substrate, said first to third buried layers being formed in different regions of said surface of said semiconductor substrate from one another, said second conductivity type being opposite to said first conductivity type;
- forming an epitaxial layer on said first to third buried layers;
- forming a first well region of said first conductivity type, a second well region of said second conductivity type and a third well region of said first conductivity type in said epitaxial layer respectively, said first to third well regions being formed on said first to third buried layers respectively, said first to third well regions having surface portions which correspond to an upper surface of said epitaxial layer respectively, wherein each of said first, second and third well regions has an impurity concentration decreasing uniformly from said surface portions to said first, second and third buried layers, respectively;
- introducing first impurities of said second conductivity type into entire said first and second well regions, to form a first doped layer of said second conductivity type and a second doped layer of said second conductivity type in said surface portions of said first and second well regions respectively;
- introducing second impurities of said first conductivity type into entire said first and second well regions so as to increase an effective impurity concentration of said first well region of said first conductivity type at the bottom of said first doped layer and decrease an effective impurity concentration of said second well region of said second conductivity type at the bottom of said second doped layer;
- forming, after the steps of introducing said first and second impurities, an insulated gate electrode of a first MISFET of said second conductivity type over said first doped layer in said first well region;
- forming, after the steps of introducing said first and second impurities, an insulated gate electrode of a second MISFET of said first conductivity type over said second doped layer in said second well region;
- forming source and drain regions of said first conductivity type of said second MISFET in said second well region at the both sides of said insulated gate electrode of said second MISFET;
- forming source and drain regions of said second conductivity type of said first MISFET in said first well region at the both sides of said insulated gate electrode of said first MISFET;
- forming a base region of said second conductivity type of a bipolar transistor in said third well region;
- and
- forming an emitter region of said first conductivity type of said bipolar transistor in said base region.