US 5,289,432 AGranted

Dual-port static random access memory cell

AssigneeInternational Business Machines Corporation

InventorsSang H. Dhong, Hyun J. Shin

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Abstract

A dual port SRAM is shown which comprises first and second word lines and first and second bit lines. A pair of semiconductor memory devices are cross coupled into a bistable circuit for storing true and complement logic levels and are coupled between common and power supply lines. A first access semiconductor is connected between the first bit line and one semiconductor memory device, and its control electrode is connected to the first word line. A second access semiconductor is connected between the second bit line and another of the semiconductor memory devices, and its control electrode is connected to the second word line. A write circuit is provided for applying write potentials to the first bit and word lines to switch the conduction states of the semiconductor memory devices. A further circuit is provided for reducing the voltage level on the power supply line when the write circuit applies the write potentials, the voltage reduction not being greater than 50% of its prereduction level, so that the potential at the second access semiconductor still exhibits a proper logic level in accordance with the memory state of the cell.

Claims6

Dependent claims

A dual port, static, random access memory cell comprising:

first and second word lines and first and second bit lines;
a pair of semiconductor memory devices, each having a first electrode and a control electrode cross connected to a first electrode of another one of said pair to create a bistable circuit for storing true and complement logic levels, said semiconductor memory devices coupled between a common potential and a power supply line connected to a power supply that provides at least a first voltage level;
a first access semiconductor connected between said first bit line and one of said semiconductor memory devices, said first access semiconductor having a control electrode connected to said first word line;
a second access semiconductor connected between said second bit line and another of said semiconductor memory devices, said second access semiconductor having a control electrode connected to said second word line;
first read/write means coupled to said first bit and word lines for applying write potentials to said first bit and word lines to switch the conduction states of said semiconductor memory devices;
and
means connected to said power supply for applying a second voltage level that is reduced in voltage level relative to said first voltage level on said power supply line when said first read/write means applies said write potentials, said second voltage level being at least 50% of said first voltage level, whereby a logic level at said second access semiconductor continues to exhibit a voltage level consistent with a predetermined logic state at said second access semiconductor.

4 more elements

Dependencies are inferred from the claim text.