US 5,289,431 AGranted

Semiconductor memory device divided into blocks and operable to read and write data through different data lines and operation method of the same

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorYasuhiro Konishi

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Abstract

In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

Claims14

Dependent claims

A semiconductor memory device comprising:

a plurality of blocks each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit lines provided corresponding to said plurality of columns;
first selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data writing operation;
second selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data reading operation;
block selecting means for selecting any of said plurality of blocks;
a plurality of write data bus means provided corresponding to said plurality of blocks each receiving write data;
a plurality of connecting means provided corresponding to said plurality of blocks each for electrically connecting said bit line selected by said first selecting means in the corresponding block to the corresponding write data bus means;
a plurality of read data bus means provided corresponding to said plurality of blocks each for externally transmitting read data;
a plurality of transmitting means provided corresponding to said plurality of blocks each for transmitting potential variation in said bit line selected by said second selecting means in the corresponding block to the corresponding read data bus means;
a plurality of read amplifier means provided corresponding to said plurality of blocks each for amplifying said potential variation transmitted by the corresponding transmitting means;
a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing all of said bit lines in the corresponding block to a predetermined potential Vb1, when the corresponding block is not selected by said block selecting means;
and
a plurality of precharging means provided corresponding to said plurality of blocks each for precharging the corresponding write data bus means to said predetermined potential, when the corresponding block is not selected by said block selecting means in data writing operation.

9 more elements

A semiconductor memory device comprising:

a plurality of blocks each including a plurality of dynamic memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit line pairs provided correspondingly to said plurality of columns;
first selecting means for selecting any of said plurality of bit line pairs in each of said blocks in a data writing operation;
second selecting means for selecting any of said plurality of bit line pairs in each of said plurality of blocks in a data reading operation;
block selecting means for selecting any of said plurality of blocks;
and
a plurality of write data line pairs provided corresponding to said plurality of blocks each for receiving write data;
wherein
each of said bit line pairs includes first and second bit lines, and
each of said write data line pairs includes first and second write data lines;
said semiconductor memory device further comprising;
a plurality of connecting means which are provided corresponding to said plurality of blocks, each for electrically connecting said first and second bit lines included in the bit line pair selected by said first selecting means to said first and second write data lines included in the corresponding write data line pair, in the corresponding block,
a plurality of read data line pairs provided corresponding to said plurality of blocks, each for externally transmitting read data,
each of said plurality of read data line pairs including first and second read data lines;
a plurality of transmitting means provided corresponding to said plurality of blocks, each for transmitting potential variation in said first and second bit lines included in the bit line pair selected by said second selecting means to said first and second read data lines included in the corresponding read data line pair, in the corresponding block;
a plurality of read amplifier means provided corresponding to said plurality of blocks, each for amplifying potential difference between said first and second read data lines included in the corresponding read data line pair;
a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing said first and second bit lines included in each of said plurality of bit line pairs in the corresponding block, to a predetermined potential, when the corresponding block is not selected by said block selecting means;
and
a plurality of precharging means provided corresponding to said plurality of blocks, each for precharging said first and second write data lines included in the corresponding write data line pair, to said predetermined potential, when the corresponding block is not selected by said block selecting means in the data writing operation.

15 more elements

A semiconductor memory device comprising:

a plurality of blocks each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit lines provided corresponding to said plurality of columns;
first selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data writing operation;
second selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data reading operation;
block selecting means for selecting any of said plurality of blocks;
a plurality of write data bus means provided corresponding to said plurality of blocks each receiving write data;
a plurality of connecting means provided corresponding to said plurality of blocks each for electrically connecting said bit line selected by said first selecting means in the corresponding block to the corresponding write data bus means;
a plurality of read data bus means provided corresponding to said plurality of blocks each for externally transmitting read data;
a plurality of transmitting means provided corresponding to said plurality of blocks each for transmitting potential variation in said bit line selected by said second selecting means in the corresponding block to the corresponding read data bus means;
a plurality of read amplifier means provided corresponding to said plurality of blocks each for amplifying said potential variation transmitted by the corresponding transmitting means;
a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing all of said bit lines in the corresponding block to a predetermined potential Vb1, when the corresponding block is not selected by said block selecting means;
and
a plurality of precharging means provided corresponding to said plurality of blocks each for precharging the corresponding write data bus means to said predetermined potential, when the corresponding block is not selected by said block selecting means in data writing operation,
said first selecting means being responsive to a selected output from said second selecting means and a control signal instructing said data writing for generating a signal selecting any one of said plurality of bit lines.

10 more elements

Dependencies are inferred from the claim text.