Address decoder which variably selects multiple rows and/or columns and semiconductor memory device using same

A semiconductor memory cell device comprising:

• a memory cell array;
• and
• a column address decoder including:
• match signal generating means responsive to an inputted column address signal to select a column of said memory cell array and a column address mask signal applied externally to mask any given bits of the inputted column address signal, having a first logical gate circuit for generating a value irrespective of a value of the inputted column address when a bit value is a designated mask value and generating an inputted column address value as it is when the bit value is a nondesignated mask value, and a second logical gate circuit for generating a value irrespective of the value of the inputted column address when a bit value is a designated mask value and generating an inverted inputted column address value when the bit value is a nondesignated mask value, and
• column address selection signal generating means responsive to a pair of the signals outputted from said first logical gate circuit and said second logical gate circuit, for generating a plurality of column address selection signals for selecting column addresses having same values at bits except masked bits as the inputted column address signal.

A semiconductor memory cell device comprising:

• a memory cell array;
• and
• a row address decoder including:
• match signal generating means responsive to an inputted row address signal to select a row of said memory cell array and a row address mask signal applied externally to mask any given bits of the inputted row address signal, having a first logical gate circuit for generating a value irrespective of a value of the inputted row address when a bit value is a designated mask value and generating an inputted row address value as it is when the bit value is a nondesignated mask value, and a second logical gate circuit for generating a value irrespective of the value of the inputted row address when a bit value is a designated mask value and generating an inverted inputted row address value when the bit value is a nondesignated mask value, and
• row address selection signal generating means responsive to a pair of the signals outputted from said first logical gate circuit and said second logical gate circuit, for generating a plurality of row address selection signals for selecting row addresses having same values as bits except masked bits as the inputted row address signal.