US 5,289,428 A · Semiconductor memory device

Abstract

A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

Claims18

Dependent claims

A semiconductor memory device comprising:

a first random memory array including a first bit line coupled to a plurality of memory cells;
a second random memory array including a second bit line coupled to a plurality of memory cells;
a serial memory array for converting parallel information from said first and second random memory arrays to serial information, including at least one register circuit for storing information from one of said memory cells included in said first and second random memory arrays;
selecting means for selecting one of said memory cells of said first random memory array;
first switching means for coupling said first bit line with said second bit line in response to selection of said one of said memory cells of said first memory array;
and
first transfer switching means for coupling said second bit line with said register circuit so that information stored in said selected memory cell of said first random memory array can be coupled to said register circuit via said second bit line.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims18