Multiport memory with write priority detector
AssigneeMotorola, Inc.
InventorsJames W. Nicholes, Douglas D. Smith
Life of this patent
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Abstract
A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.
Claims13
A multiport memory circuit, comprising:
- a memory cell having first and second data inputs and having first and second enable inputs receiving first and second enable signals, said first enable signal allowing said first data input to receive data for storage in said memory cell, said second enable signal allowing said second data input to receive data for storage in said memory cell;
- and
- a write priority detector coupled for receiving first and second address signals and providing said first and second enable signals respectively, said write priority detector including,
- (a) a first inverter having an input receiving said first address signal and having an output,
- (b) a first logic gate having first and second inputs and an output, said first input being coupled to said output of said first inverter, said output providing said first enable signal,
- (c) a second logic gate having first and second inputs and an output, said first input being coupled to said output of said first inverter, said second input being coupled to said output of said first logic gate, said output being coupled to said second input of said first logic gate, and
- (d) a first transistor having a gate, a drain and a source, said drain being coupled to said input of said first inverter, said gate receiving said second enable signal, said source being coupled to said second input of said first logic gate.
A write priority detector in a memory circuit, comprising:
- a first logic gate having first and second inputs and an output, said first input receiving a maxi signal of a first address signal, said second input receiving a block signal of said first address signal;
- a first inverter having an input coupled to said output of said first logic gate and having an output;
- a second logic gate having first and second inputs and an output, said first input being coupled to said output of said first inverter, said output providing a first enable signal;
- a third logic gate having first and second inputs and an output, said first input being coupled to said output of said first inverter, said second input being coupled to said output of said second logic gate, said output being coupled to said second input of said second logic gate;
- and
- a first transistor having a gate, a drain and a source, said drain being coupled to said output of said first logic gate, said gate receiving a second enable signal, said source being coupled to said second input of said second logic gate.
Dependencies are inferred from the claim text.