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US 5,289,426 AGranted
Dual port memory having address conversion function
AssigneeKabushiki Kaisha Toshiba
InventorsKeiji Namimoto, Hiromasa Hayashi
Life of this patent
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Abstract
A dual port memory device has two input/output ports. These ports involve address circuits having different coordinate conversion tables. The dual port memory device can quickly respond to access signals prepared on different coordinates and is applicable for graphics processing, etc., which require high-speed memories.
Claims14
A dual port memory comprising:
- a memory array, having a plurality of storing locations for storing data in a two-dimensional array, any storing location of said memory array being accessed by either of first and second inner address signals in accordance with a memory accessing two dimensional coordinate system, respectively responsive to first and second address signals different from each other in accordance with first and second two-dimensional coordinate systems;
- a first address circuit associated with said memory array for receiving said first address signal, said first address signal indicating a first particular storing location in said two-dimensional array in accordance with said first coordinate system, and for converting said first address signal to said first inner address signal to be applied to said memory array in order to access said first particular storing location;
- and
- a second address circuit associated with said memory array for receiving said second address signal, said second address signal indicating a second particular storing location in said two-dimensional array in accordance with said second coordinate system, and for converting said second address signal to a second inner address signal to be applied to said memory array in order to access said second particular storing location.
1 more element
A method of accessing data located in a two-dimensional array, the method comprising the steps of:
- storing said data in a memory array having a plurality of storing locations accessible by either of first and second inner address signals in accordance with a memory accessing two dimensional coordinate system, respectively responsive to first and second address signals different from each other in accordance with first and second two-dimensional coordinate systems;
- wherein accessing said data with said first address signal comprises the steps of:
- receiving said first address signal in a first address circuit associated with said memory array, said first address signal indicating a first particular storing location in said two-dimensional array in accordance with said first coordinate system;
- converting said first address signal to said first inner address signal;
- applying said first inner address signal to said memory array in order to access said first particular storing location;
- and
- wherein accessing said data with said second address signal comprises the steps of:
- receiving said second address signal in a second address circuit associated with said memory array, said second address signal indicating a second particular storing location in said two-dimensional array in accordance with said second cordinate system;
- converting said second address signal to a second inner address signal;
- and
- applying said second inner address signal to said memory array in order to access said second particular storing location.
8 more elements
Dependencies are inferred from the claim text.