Semiconductor device having dummy wiring pattern therein and manufacturing method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTomoharu Mametani
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Abstract
A are a semiconductor memory device excellent memory characteristics of which can be obtained without deteriorating a characteristic of a transistor for use in a peripheral circuit even when a memory cell array region and a peripheral circuit region differ from each other in wiring pattern density and a manufacturing method therefor. The semiconductor memory device includes a dummy pattern formed between and at predetermined distance from gate electrodes of a transfer gate transistor in the peripheral circuit region. As a result, precision in dimension of the gate electrode in the peripheral circuit portion is improved to achieve excellent memory characteristics without deteriorating the transistor
Claims11
A semiconductor memory device formed on a semiconductor substrate having at least one memory cell array region wherein a plurality of memory cells each including a first transistor and a capacitor are formed and a peripheral circuit region wherein a plurality of second transistors for use in a peripheral circuit are formed, said semiconductor memory device comprising:
- a pair of first gate electrode layers arranged in parallel and at predetermined distance from each other in said memory cell array region, each pair constituting said first transistor,
- a second gate electrode layer and a dummy wiring layer arranged in parallel and at predetermined distance from each other in said peripheral circuit region to constitute one of said second transistors for use in a peripheral circuit, wherein
- spacing between said paired first gate electrode layers formed in said memory cell array region is approximately the same as spacing between the second gate electrode layer and the dummy wiring layer formed in said peripheral circuit region.
Dependencies are inferred from the claim text.