Static random access memory device with high speed differential amplifier coupled with digit line pair through capacitors

A static type random access memory device fabricated on a single semiconductor chip, comprising:

• a) a plurality of memory cells arranged in rows and columns, and respectively storing data bits each in the form of a differential voltage level;
• b) a plurality of digit line pairs respectively associated with the columns of said plurality of memory cells, and operative to propagate differential voltage levels respectively indicative of data bits;
• c) a plurality of word lines respectively associated with the rows of said plurality of memory cells, and selectively driven to an active level for coupling said plurality of digital lines with the memory cells associated therewith;
• d) a plurality of sense amplifier circuits respectively associated with said plurality of digit line pairs, and each responsive to the differential voltage level on the associated digit line pair so as to rapidly develop a differential voltage level indicative of one of the data bits on the associated digit line pair between a pair of internal nodes provided therein;
• e) a precharging circuit coupled with said plurality of digit line pairs for precharging said plurality of digit line pairs to one of high and low voltage levels;
• f) a plurality of coupling means capactively coupled between said plurality of digit line pairs and pairs of input nodes of said plurality of sense amplifier circuits;
• and
• g) an intermediate voltage producing means coupled with said pair of internal nodes of each sense amplifier circuit for precharging said pair of internal nodes to an intermediate voltage level between said high and low voltage levels.