Memory apparatus with built-in parity generation

A memory circuit for generating block parity from multiple bytes of data comprising:

• a memory array for storing a plurality of bits, said memory array having address inputs and data input and output lines;
• a logic circuit having first inputs coupled to said memory array data output lines for receiving a first data byte and second inputs coupled to external data input lines for receiving a second data byte, said logic circuit producing a parity byte from the combination of said first and second data bytes;
• and
• latching means, coupled between an output of said logic circuit and said memory array data input lines, for isolating said parity byte from said first and second data bytes;
• whereby parity generation is done with said memory circuit remotely from an external processor.

A memory circuit comprising:

• a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines;
• an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines;
• latching means, coupled between an output of said logic circuit and said memory array data input/output lines;
• and
• control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input lines in a second cycle.

A memory circuit comprising:

• a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines;
• an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines;
• latching means, coupled between an output of said logic circuit and said memory array data input/output lines;
• transceiver means, coupled between said memory array data input/output lines and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input/output lines in response to a transceiver disable control signal;
• and
• control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input/output lines in a second cycle;
• said control means having a transceiver control output coupled to said transceiver means for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal;
• said control means further comprising a read input line and a write input line, said control means generating a transceiver enable control signal on said transceiver control output in response to a read signal on said read input line or a write signal on said write input line.