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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima
Estimating the term…
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
A semiconductor memory device with a redundancy circuit, comprising:
A semiconductor memory device with a redundancy circuit, comprising:
A semiconductor memory device with a redundancy circuit, comprising:
An on-chip semiconductor memory device with a redundancy circuit, comprising:
A method of operating a semiconductor memory device including a memory cell array including a plurality of blocks (1a, 1b) each including a plurality of memory cells (MC) and a plurality of redundancy circuit means (2a, 2b, 5a, 5b) which are provided in correspondence to said plurality of blocks (1a, 1b) for replacing a part of the corresponding blocks, comprising the steps of:
A semiconductor memory device with a redundancy circuit, comprising:
Dependencies are inferred from the claim text.