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AssigneeHitachi, Ltd.
InventorsHidetoshi Iwai, Masamichi Ishihara, Kazuya Ito, Wataru Arakawa, Yoshinobu Nakagome
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An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.
A semiconductor integrated circuit device to prevent leakage current flow through defective circuit elements that are not used in an internal circuit characterized in that the internal circuit may be selectively changed by cutting and/or connecting predetermined wirings which are formed on a semiconductor substrate and which are connected to the defective circuit elements to prevent leakage current flow through said defective circuit elements.
Wiring correction equipment to prevent leakage current flow through defective circuit elements that are not used in an internal circuit characterized in that predetermined wirings formed on a semiconductor substrate of a semiconductor integrated circuit device, which wirings are connected to the defective circuit elements, are cut and/or connected on the basis of the wiring correction data obtained by predetermined test equipment to prevent leakage current flow through said defective circuit elements.
A semiconductor integrated circuit device to prevent leakage current flow through defective circuit elements that are not used in an internal circuit including a plurality of normal circuit elements, a plurality of said defective circuit elements, and a plurality of redundant circuit elements to replace the defective circuit elements, wherein the normal circuit elements, the defective circuit elements and the redundant circuit elements are connected in a predetermined internal composition by wirings, wherein said wirings include predetermined cutting points to permit cutting of said wiring coupled to said defective circuit elements to thereby prevent leakage current through said defective circuit elements.
A method for preventing leakage current through defective circuit elements in a semiconductor integrated circuit device which includes redundant circuit elements to replace the defective circuit elements, wherein said method comprises:
Dependencies are inferred from the claim text.