Dynamic semiconductor memory device with high-speed serial-accessing column decoder

A dynamic memory device comprising:

• an array of rows and columns of memory cells each of which includes a storage capacitor and a MOS transistor;
• control lines connected to the rows of memory cells;
• data transfer lines associated with the columns of memory cells;
• sense amplifiers having inputs connected to each column;
• transfer-gate devices having control electrodes, said transfer-gate devices being arranged at outputs of said sense amplifiers, for selectively turning on to allow a binary information bit appearing on a corresponding data transfer line to pass therethrough;
• row decoder means connected to said control lines, for specifying a selected control line in response to an external address input;
• column decoder means connected to said transfer-gate devices, for selectively activating said transfer-gate devices to designate a selected data transfer line in response to an input column address externally supplied thereto;
• said column decoder means causing, when turning on a certain transfer-gate device associated with said selected data transfer line, a specific transfer-gate device which neighbors on said selected data transfer line and which is associated with another data transfer line to be serially accessed next to turn on before a column address of said specific transfer-gate device actually arrives at said column decoder means;
• latch means connected to outputs of said transfer-gate devices, for receiving information bits transferred via said certain transfer-gate device and said specific transfer-gate device, and for temporality latching the information bits;
• and
• means connected to said latch means, for sequentially generating the latched information bits in a serial manner.

A dynamic memory device comprising:

• an array of memory cells in rows and columns;
• redundant memory cells in spare columns;
• row decoder means connected to the rows of memory cells, for selecting one of the rows of memory cells in response to a row address signal input;
• column decoder means connected to the columns of memory cells and said spare columns, for selecting a certain column from among the columns including said spare columns in response to a column address signal input;
• said column decoder means comprising activation means for, when activating said certain column, also activating a column adjacent to said certain column before actual arrival of a corresponding column address thereof, wherein said column decoder means further comprises:
• spare column selector means for specifying among said spare columns a proper column that replaces a damaged column;
• and
• spare column decoder means connected to said spare column selector means, for potentially activating said proper column before a corresponding address thereof is externally supplied.

A dynamic memory device comprising:

• an array of memory cells in rows and columns;
• row decoder means connected to the rows of memory cells, for selecting one of said rows of memory cells in response to a row address signal supplied thereto;
• sense amplifiers connected to the columns of said memory cells, for outputting sensed data signals;
• column-select line means connected to every pair of said sense amplifiers, for selecting a first number of neighboring columns simultaneously;
• data transfer line means connected to said sense amplifiers, for sending forth the outputs of said sense amplifiers;
• said data transfer line means comprising a second number of line segments which include a first group of line segments associated with alternate ones of said columns of said memory cells and a second group of line segments associated with the rest of said columns of said memory cells, each of the first and second groups of line segments having the first number of parallel line segments;
• column decoder means connected to said column-select line means, for designating a certain column in response to an input column address signal externally supplied thereto, and for, when activating said certain column, potentially activating a column adjacent to said certain column before a corresponding column address thereof actually arrives, thereby allowing output signals of two adjacent pairs of sense amplifiers to be developed simultaneously onto said second number of line segments;
• and
• output means connected to said data transfer line means, for alternately selecting the sensed data signals on said first group of line segments and those on said second group of line segments, and for serially and externally sending forth the second number of selected data signals.

A serial-access memory system comprising:

• an array of memory cells arranged in rows and columns;
• row decoder means connected to the rows of memory cells for selecting one of the rows of memory cells in response to a row address signal externally supplied thereto;
• column decoder means connected by column select lines to the columns of memory cells, for serially decoding columns in a predetermined order by designating a certain column presently selected in response to an input column address signal externally supplied thereto;
• and
• said column decoder means comprising column activation means for potentially activating a column select line corresponding to the selected column in one of a series of read cycles defined by an external column address strobe signal which potentially changes alternately or toggles between first and second levels, and for simultaneously activating or preactivating another column select line neighboring thereto during said one cycle, thereby allowing said another column select line to be completed in activation before the column strobe signal enters a subsequent read cycle.