Semiconductor memory circuit device having memory cells constructed on a Bicmos gate array
AssigneeKabushiki Kaisha Toshiba
InventorsHiroyuki Hara, Yoshinori Watanabe
Life of this patent
Estimating the term…
Abstract
A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array includes amplifying means constituted by a bipolar transistor connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means amplifies the potential level of readout data of the memory cell and output the same to an output line, thus enhancing the driving ability of the output line and reducing the whole readout time for reading out data from the memory circuit.
Claims8
A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array, comprising:
- basic cells in a matrix on a substrate in a gate array memory cell configuration by the Master slice approach and including:
- an input line adapted to receive write-in data;
- input switching means having a first end coupled to said input line, and a second end;
- a write-in signal line adapted to receive a write-in signal used as a switching control signal for controlling said input switching means;
- a data holding section having an end coupled to the second end of said input switching means, and an output, for holding the write-in data from said input line via said input switching means;
- output switching means including a current path having a first end coupled to the output of said data holding section, and a second end;
- a readout signal line adapted to receive at least one readout signal used as a switching control signal for controlling said output switching means;
- amplifying means having an input coupled to the second end of said output switching means, and an output;
- and
- an output line coupled to the output of said amplifying means, for outputting readout data amplified by said amplifying means.
An apparatus, comprising:
- a plurality of memory cells in an array configuration, each memory cell including a respective
- input switching means including a control input, and a current path having a first end, and a second end,
- a data holding section having an input coupled to the second end of said input switching means, and an output,
- an output switching means including a control input, and a current path having a first end coupled to the output of said data holding section, and a second end, and
- an amplifying means having an input terminal coupled to the second end of said current path included in said output switching means.
Dependencies are inferred from the claim text.