Self-timed content addressable memory access mechanism with built-in margin test feature

In a memory device having a compare array, wherein the compare array includes means for receiving first input data and a first clock signal, and for processing the first input data to generate a first output signal after the compare array receiving means receives the first clock signal, a system for determining when the first output signal is valid, said system comprising:

• means for storing a data word having a first bit equal to a first predetermined value and M second bits each equal to the first predetermined value, wherein M is an integer greater than zero;
• receiver means for receiving the first clock signal and second input data, the second input data having a first bit equal to a second predetermined value and M second bits each equal to the first predetermined value;
• means for charging a second output signal to a first predetermined level;
• a first comparator, coupled to the storing means, the receiver means, and the charging means, for comparing the first bit of the second input data to the first bit of the data word after the receiver means receives the first clock signal, said first comparator also for discharging the second output signal from the first predetermined level to a second predetermined level when the first bit of the second input data does not match the first bit of the data word;
• M second comparators, coupled to the storing means, the receiver means, and the charging means, for comparing the second bits of the second input data to the second bits of the data word after the receiver means receives the first clock signal, said M second comparators also for discharging the second output signal from the first predetermined level to the second predetermined level when the second bits of the second input data does not match the second bits of the data word;
• and
• means, coupled to the first and second comparators, for processing the second output signal to generate a second clock signal, the first output signal being valid when the second clock signal is generated;
• wherein the first comparator operates to discharge the second output signal since the first bits of the second input data and the data word never match, and wherein the second comparators do not operate to discharge the second output signal since the second bits of the second input data and the data word always match.