Single-flux-quantum multiply-accumulator

A serial multiplier for multiplying two n-bit numbers comprising:

• a shift register having a total of n destructive read out cells, each of said cells initially containing a separate bit of a first multiplicand and one of said cells serving as an output cell;
• a string of (2n-1) non-destructive read out cells, each of said non-destructive read out cells having a read out gate connected to the output cell of the shift register, each of the first n non-destructive read out cells of said string of (2n-1) non-destructive read out cells containing a separate bit of a second multiplicand;
• timing means for shifting said bits of said first multiplicand through said shift register whereby each bit of said first multiplicand is serially multiplied with said series of bits of said second multiplicand to form a plurality of partial products;
• a string of 2n T flip-flop cells, each of said T flip-flop cells having an input for receiving a bit from each of said partial products and having a carry path to the next adjacent T flip-flop cell;
• and
• said timing means moving each bit of said second multiplicand to the next adjacent non-destructive read out cell after each multiplication of a bit of said first multiplicand with said series of bits of said second multiplicand such that said string of 2n T flip flops contains a full product of said first and second multiplicands.