Small-sized low power consumption multiplication processing device with a rounding recording circuit for performing high speed iterative multiplication

A multiplication processing device comprising:

• recoding circuit means for recoding a multiplier;
• and
• recording data setting means for subtracting a value B represented by using a redundant binary number, which is equal to Bb .+-..alpha..multidot.2.sup.-k (Bb is represented by a binary number having a non-zero value at a digit of which the order is equal to or higher than that corresponding to 2.sup.-j ;
• (1/2).ltoreq..alpha..ltoreq.1;
• and i, j.ltoreq.k) if converted into a binary number, from a predetermined constant A represented by a binary number which has a non-zero value at a digit of which the order is equal to or higher than that corresponding to 2.sup.-1 and for outputting the result of the subtraction to the recoding circuit means, wherein said recoding data setting means sets (A-Bb) at each of from the most significant digit of the result of the subtraction to a digit corresponding thereof to 2.sup.-L (L is the maximum value of i and j) and sets 0 at each of from a digit thereof corresponding to 2-(L+1) to digit thereof corresponding to 2.sup.-(L+m) (1.ltoreq.m.ltoreq.k-L) and sets a value, which is obtained by inverting the sign of a value set at a digit of the value B corresponding to 2.sup.-(L+m), at a digit of the result of the subtraction corresponding to 2.sup.-(L+m+) if a value set at a digit of the value B corresponding to 2.sup.-(L+m) is 0 and sets the value, which is set at the digit of the value B corresponding to 2.sup.-(L+m+1), at the digit of the result of the subtraction corresponding to 2.sup.-(L+m+1) if the value set at the digit of the value B corresponding to 2.sup.-(L+m) is other than 0 and sets the values, which are respectively obtained by inverting the signs of the values set at the digits of the value B corresponding to values equal to and less than 2.sup.-(L+m+2), at digits of the result of the subtraction corresponding to values equal to and less than 2.sup.-(L+m+2) and outputs the set value of the result of the subtraction to said recoding circuit means.