Data rearrangement processing apparatus for digital video signal recording apparatus

In a recording apparatus for recording on a recording medium a digital video signal comprising successive samples, said samples being arrayed in successive lines and fields of said video signal, said apparatus including channel allocation means for allocating alternate ones of said samples of each line of said video signal to a first recording channel and a second recording channel respectively and recording means for recording samples of said first and second channels on respectively different tracks of said recording medium, a data rearrangement apparatus coupled between said channel allocation means and said recording means, said data rearrangement apparatus comprising for each of said channels:

• field memory means (103) wherein a two-dimensional array of memory locations is defined by two-dimensional memory addresses;
• data shuffling means (101) for assigning to said samples of said channel of one field of said digital video signal, within each of successive lines of the video signal, respectively block numbers (Oblk) each specifying one of a fixed plurality of blocks, and respective intra-block addresses (Hd),
• for executing on said blocks respectively different shuffling operations based on said block numbers and block addresses to obtain respective converted intra-block addresses (Obyt) and for assigning the respective converted intra-block addresses to respective samples,
• and for outputting said samples in synchronism with outputting corresponding ones of said block numbers and converted intra-block addresses;
• write address generating circuit means (104) respective to said converted intra-block addresses (Obyt) and block numbers (Oblk) for generating corresponding memory addresses (Row, Col) for writing said samples outputted from said intra-line shuffling circuit means into said field memory means along a first direction of said array;
• and
• read address generating circuit means (105) for generating successive memory addresses (Row, Col) for successively reading out from said field memory means along a second direction of said array, each of a plurality of segments of said samples, said segments being stored in respective regions of said field memory means, and for supplying said samples thus read out to said recording means at timings such that said samples of respective ones of said segments are written onto respectively different ones of said tracks of said recording medium;
• said shuffling operations being respectively predetermined such that adjacent samples of a same line and same channel in a field are written into respectively different ones of said regions.

In a recording apparatus for recording on a recording medium a digital video signal comprising successive samples, said samples being arrayed in successive lines and fields of said video signal, said apparatus including channel allocation means for allocating alternate ones of said samples of each line of said video signal to a first recording channel and a second recording channel respectively and recording means for recording samples of said first and second channels on respectively different tracks of said recording medium, the improvement comprising:

• a data rearrangement apparatus coupled between said channel allocation means and said recording means to enable recording and reproducing successive digital samples alternately sent to the first and second recording channels by respectively different ones of two pairs of heads, said data rearrangement apparatus comprising for each of said channels:
• field memory means (103) wherein a two-dimensional array of memory locations is defined by two-dimensional memory addresses;
• data shuffling means (101) for assigning to said samples of said channel of one field of said digital video signal, within each of successive lines of the video signal, respectively block numbers (Oblk) each specifying one of a fixed plurality of blocks, and respective intra-block addresses (Hd),
• for executing on said blocks respectively different shuffling operations based on said block numbers and block addresses to obtain respective converted intra-block addresses (Obyt) and for assigning the respective converted intra-block addresses to respective samples,
• and for outputting said samples in synchronism with outputting corresponding ones of said block numbers and converted intra-block addresses;
• write address generating circuit means (104) respective to said converted intra-block addresses (Obyt) and block numbers (Oblk) for generating corresponding memory addresses (Row, Col) for writing said samples outputted from said intra-line shuffling circuit means into said field memory means along a first direction of said array;
• and
• read address generating circuit means (105) for generating successive memory addresses (Row, Col) for successively reading out from said field memory means along a second direction of said array, each of a plurality of segments of said samples, said segments being stored in respective regions of said field memory means, and for supplying said samples thus read out to said recording means at timings such that said samples of respective ones of said segments are written onto respectively different ones of said tracks of said recording medium;
• said shuffling operations being respectively predetermined such that adjacent samples of a same line and same channel in a field are written into respectively different ones of said regions.