US 5,289,310 A · A frame line memory control circuit and method for controlling storage of video data of a video signal

Abstract

A circuit and method of controlling the write and read operations of video data onto a line memory without occurrence of any data collision between odd fields occurs with the line memory providing a thermal print head of a video printer with printing data, in a frame-by-frame printing system. The line memory is provided with a frame-by-frame reading and writing system upon storing the video data therein and upon providing printing data to a thermal print head of the video printer. The video data of a first odd field corresponding to a first line during a first odd field period and the video data of a first even field corresponding to the first line during a first even field period are written into the line memory. The video data of a second odd field corresponding to a second line during a second odd field period and concurrently thereto, a read out is enabled for the first odd and even field video data corresponding to the first line from the line memory to therefrom print out the corresponding video data in the video printer. The consecutive reading, writing, and printing steps are repeated until completing all the scanning lines on a single video screen.

Claims20

Dependent claims

A frame line memory control circuit for controlling a frame line memory for storing video data, the control circuit comprising:

a controller generating a multiplicity of control signals;
analog-digital conversion means for converting an analog video signal from a video processor to corresponding digital video data;
latch means for temporarily storing said video data from said conversion means during printing operations;
memory means comprising said line memory for storing said video data and providing said video data upon request from the controller;
first switching means connectable to said conversion means and said latch means, for selectively transferring said video data from one of said conversion means and said latch means to said memory means, said first switching mean being under control of said controller;
write address counter means for providing a write address to store said video data in said memory means under control of said controller;
first logic gate means for producing a first gate signal to enable operation of said latch means and said write address counter means;
read address counter means for providing a read address to retrieve said video data from said memory means, said read address counter means being under control of said controller;
second logic gate means for producing a second gate signal;
second switching mans connectable to said read address counter means and said write address counter means, for selectively providing one of said read address and said write address to said memory mean in dependence upon said second gate signal from said second logic gate means;
and
a third switching means connectable to said write address counter means, for transferring a selected one of said write addresses from said write address counter means to said second switching means, said third switching means being under control of said controller;
whereby writing and reading operations of the video data in the memory means are carried out line by line.

10 more elements

A frame line memory control circuit for controlling storage of video data of a video signal, said circuit comprising:

first memory for storing odd field data and even field data corresponding to a first line of said video data and odd field data and even field data corresponding to a second line of said video data;
second memory for storing the odd field data corresponding to the second line prior to the odd field data corresponding to the second line being store din the first memory;
first switching means for transferring said odd field data corresponding to the first line to the first memory, then transferring said even field data corresponding to the first line to the first memory, then transferring said odd field data corresponding to the second line from the second memory to the first memory, then transferring said even field data corresponding to the second line to the first memory, said transferring of the odd field data corresponding to the second line occurring in dependence upon a fourth pulse of a plurality of pulses of a horizontal synchronizing signal of said video signal, said fourth pulse occurring between reading gradations of said odd field data corresponding to the first line and said even field data corresponding to the first line of video data stored in the first memory.

Dependencies are inferred from the claim text.

A frame line memory control circuit and method for controlling storage of video data of a video signal

Life of this patent

A frame line memory control circuit and method for controlling storage of video data of a video signal

Life of this patent

Abstract

Claims20