Transparent enable test circuit
AssigneeUnisys Corporation
InventorsDuane A. Schroeder, David M. Hime
Life of this patent
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Abstract
A test circuit for two level latches on an integrated circuit to be tested includes a test enable driver circuit coupled to a third level switch which is connected in series between the latches to be tested and a low voltage source. The third level switch converts the two level latches to be tested into a buffer such that data applied as an input to the two level latches appears in identical form as data at the output pin of the integrated circuit chip.
Claims12
A transparent enable mode test circuit for testing two level switch devices, comprising:
- an integrated circuit chip device comprising a plurality of two level transistorized switches, having first and second levels to be tested,
- each of said switches to be tested having a data input line for latching data therein,
- each of said switches to be tested being coupled to an output pin on said chip for detecting the state condition of said two level switches,
- transparent enable switch means coupled between said second level of said two level transistorized switches to be tested and a voltage current source for said two level switches,
- said transparent enable switch means having input transistor means and reference transistor means,
- a test enable circuit having an output coupled to the input of said input transistor means of said transparent enable switch means, whereby
- a first level enable test signal applied to said test enable circuit maintains said two level switch in its fixed state and it is enabled to be operable in a transparent mode.
A method of testing two level transistorized switch device of the type having first and second levels and a voltage current source on a integrated circuit ship, comprising the steps of:
- connecting a third level switch device between the second level of the switch device to be tested and its voltage current source,
- providing a test enable circuit at the input of said chip,
- coupling the output of said test enable circuit to said input of said third level switch device,
- applying a first level signal to said test enable circuit so that said two level switch device is placed in a high state, whereby said two level switch device is placed in a high state, whereby said two level switch device is placed in a transparent mode so that said two level switch device passes data applied to its input directly to the output of said two level device.
Dependencies are inferred from the claim text.