US 5,289,116 AGranted

Apparatus and method for testing electronic devices

AssigneeHewlett-Packard Company

InventorsJun Kurita, Kiyoyasu Hiwada, Nobuyuki Kasuga, Yoichiro Yamada, Shigeru Kuwano, Keita Gunji, Tomoya Yamazaki

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Abstract

An apparatus 1 for testing mixed signal electronic devices (i.e., devices, such as LSI devices, whose input/output signals include direct current signals, digital signals and analog signals, where the time relationship between the various input and output signals may be either synchronous or asynchronous) includes a master clock subsystem (MCLK-SS) 11, a subsystem group comprised of a digital master subsystem (DM-SS) 12, a digital slave subsystem (DS-SS) 13, a waveform generator subsystem (WG-SS) 14, a waveform digitizer subsystem (WD-SS) 15, a time measuring module (TMM) 16, and a direct current subsystem (DC-SS) 17, and an interfacing test head 18. The MCLK-SS 11 receives a master clock from a timing generator 21 or DSP 23 of the device under test (DUT) 186 and generates a first master clock MCLK1 and a second master clock MCLK2, each of which is synchronized with the master clock from the DUT. A reference clock generator 111, which receives the output of the buffer 181, supplies a standard clock to the first and second clock generators 112, 113, which in turn generate the first and second master clock signals.

Claims17

Dependent claims

An apparatus for testing mixed signal electronic devices, comprising:

(a) test head means for sending/receiving test signals to/from a device under test (DUT);
(b) master clock means, coupled to said test head means, for receiving at least one signal from said DUT, for generating a first master clock signal at a first frequency f.sub.1 and a second master clock signal at a second frequency f.sub.2, wherein the ratio f.sub.1 /f.sub.2 is a rational number and is selected to simulate an asynchronous operation of the DUT, and said first and second master clock signals are synchronized to the signal received from the DUT, and including timing handler means for detecting a coincidence of signal transitions of said master clock signals and generating a coincidence signal indicative of said coincidence;
(c) digital master means, coupled to said test head means and said master clock means, for sending preprogrammed digital signal patterns to said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(d) digital signal means, coupled to said test head means, for measuring digital signals from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(e) waveform generator means, coupled to said test head means, for sending analog signals to said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(f) waveform digitizer means, coupled to said test head means, for measuring analog signals from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
and
(g) direct current means, coupled to said test head means, for measuring direct current characteristics of said DUT by sending/receiving direct current signals to/from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals.

5 more elements

An apparatus for testing mixed signal electronic devices, comprising:

(a) test head means for sending/receiving test signals to/from a device under test (DUT);
(b) master clock means, coupled to said test head means, for receiving at least one signal from said DUT, for generating a first master clock signal at a first frequency f.sub.1 and a second master clock signal at a second frequency f.sub.2, wherein the ratio f.sub.1 /f.sub.2 is a rational number and said first and second master clock signals are synchronized to the signal received from the DUT, and including timing handler means for detecting a coincidence of signal transitions of said master clock signals and generating a coincidence signal indicative of said coincidence;
(c) digital master means, coupled to said test head means and said master clock means, for sending preprogrammed digital signal patterns to said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(d) digital signal means, coupled to said test head means, for measuring digital signals from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(e) waveform generator means, coupled to said test head means, for sending analog signals to said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(f) waveform digitizer means, coupled to said test head means, for measuring analog signals from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
(g) direct current means, coupled to said test head means, for measuring direct current characteristics of said DUT by sending/receiving direct current signals to/from said DUT in synchronism to a selected one of said master clock signals or a selected combination of said master clock signals;
and
(h) control means for providing test sequences for testing the DUT to the digital master means, digital signal means, waveform generator means, waveform digitizer means and direct current means,
wherein said digital master means, digital signal means, waveform generator means, waveform digitizer means, and direct current means each further comprises sequencer means for conducting test sequences without intervention of said control means after said sequences are received from said control means;
and wherein the sequencer means in said digital master means includes means for controlling the other sequencer means, and is responsive to said coincidence signal to change the sequences of the other sequencer means within one clock cycle.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/952,469Filed 28 Sep 1992 · continuation
Priority: JP 2-14363831 May 1990
Granted: 22 Feb 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G01R 31/3167
Testing of electronic circuits, e.g. by signal tracer: testing of combined analog and digital circuits
G01R 31/31922
Stimuli generation or application of test patterns to the device under test [DUT]: timing generation or clock distribution
G01R 31/3193
Tester hardware, i.e. output processing circuits: with comparison between actual response and known fault free response
G01R
Measuring electric variables