Output circuit with buffer

An output circuit comprising:

• a buffer including
• a first transistor which receives at a gate thereof a periodic input voltage;
• a second transistor, said first and second transistors being connected in series across a first level voltage and a second level voltage lower than said first level voltage, a junction of said first and second transistors being connected to an output terminal;
• and
• a third transistor whose drain and source are connected to said output terminal and said second level voltage respectively, a gate of said third transistor receiving a periodical pulse signal for setting said third transistor to an ON state for discharging a load connected to said output terminal therethrough;
• and
• means for applying, to a gate of said second transistor, a first voltage for said second transistor to serve as a bias transfer for charging said load connected to said output terminal with a voltage corresponding to said input voltage, and a second voltage greater than said first voltage for said second transistor to serve as a discharge transistor for discharging said load,
• said periodical pulse signal having a pulse width sufficient to discharge said load to a residual level greater than said second level voltage in order that the time required for charging said load again according to the level of said periodic input voltage is reduced.