MOS operational amplifier circuit

An operational amplifier circuit composed of MOS FETs comprising:

• a differential amplifier circuit having first and second input terminals and a first node, for outputting a first signal having a voltage level proportional to a difference between a voltage level of a first differential signal applied to said first input terminal and a voltage level of a second differential signal applied to said second input terminal;
• a first amplifying circuit for amplifying said first signal and simultaneously shifting the voltage level of said first signal;
• a second amplifying circuit for amplifying said first signal;
• a first conductive MOS transistor whose conductive state is controlled by said first signal amplified by said first amplifying circuit;
• a second conductive MOS transistor whose conductive state is controlled by said first signal amplified by said second amplifying circuit;
• and
• an output terminal connected between said first conductive MOS transistor and said second conductive MOS transistor.

An operational amplifier circuit composed of MOS FETs comprising:

• a first power source terminal having a first power voltage level;
• a second power source terminal having a second power voltage level;
• first, second, third and fourth nodes;
• first and second input terminals;
• an output terminal;
• a differential amplifier circuit, connected to said first and second power source terminals, said first and second input terminals and said first node, for outputting a first signal having a voltage level proportional to the difference between voltage levels applied to said first and second input terminals;
• a level shift circuit connected to said first and second power source terminals and said first node and said second node, for outputting a second signal which is obtained by shifting the voltage level of the first signal;
• a first amplifier circuit connected to said first and second power source terminals, said second and third nodes and a first MOS FET of a first conductivity type having a source connected to said first power source terminal, a gate and a drain commonly connected to said third node for amplifying the second signal and outputting a third signal to said third node corresponding to the amplified second signal;
• a second amplifier circuit coupled to said first and second power source terminals, said first and fourth nodes and a second MOS FET of a second conductivity type having a source connected to said second power source terminal, a gate and a drain commonly connected to said fourth node for amplifying the first signal and outputting a fourth signal to said fourth node corresponding to the amplified first signal;
• and
• an output circuit coupled to said first and second power source terminals, said third and fourth nodes, said output terminal, a third MOS FET of the first conductivity type having a source connected to said first power supply terminal, a gate connected to said third node and a drain connected to said output terminal and a fourth MOS FET of the second conductivity type having a source connected to said second power source terminal, a gate connected to said fourth node and a drain connected to said output terminal for outputting a fifth signal to said output terminal in response to the third and fourth signal.