BICMOS input buffer circuit with integral passgate

An input buffer circuit constructed for delivering output signals of high and low potential levels at an output in response to data signals at a data signal input, bipolar transistor output pullup and output pulldown for sourcing and sinking current at the output, a bipolar input transistor coupled to the input, and a transistor phase splitter coupled to the bipolar transistor output pullup and pulldown, and to the bipolar input transistor, for controlling the respective conducting states of the bipolar transistor output pullup and pulldown in response to data signals at the input, comprising:

• a CMOS passgate circuit coupled in the input buffer circuit between the bipolar input transistor and the bipolar transistor output pullup and pulldown, said CMOS passgate circuit having latch enable inputs for operating the input buffer circuit in transparent and blocking modes in response to latch enable signals at the latch enable inputs for respectively passing data signals from the data signal input to the output in the transparent mode and blocking data signals at the data signal input from propagating to the output in the blocking mode.

The BICMOS input buffer circuit of claim 13 wherein the first and third passgate transistors are coupled to a first node, and the first node is coupled to a base node of the transistor output pullup through a passgate resistor to reduce capacitance at said base node.