Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorNobuaki Ohtsuka
Life of this patent
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Abstract
The stress applied to a gate insulation film can be reduced by raising the potentials of the source and drain terminals of input gate transistors whose gate are applied with a high potential to a Vcc level or the like, when a programming high potential (V.sub.PP) or a high potential for tri-state control is applied to an external input terminal of an input-stage circuit of an EPROM. Therefore, occurrence of problems of the reliability such as TDDB can be prevented and thus a highly reliable nonvolatile semiconductor memory device can be provided. Further, the elements can be miniaturized to increase the capacity of the nonvolatile semiconductor memory device, without scaling the conventional programming high potential and the high potential for tri-state control.
Claims12
An input-first stage circuit for use in a semiconductor device, comprising:
- an input terminal for receiving an externally-applied input signal, the externally-applied input signal having at least a high potential and a low potential;
- a MOS transistor having a source, a drain, and a gate coupled to said input terminal and insulated from a channel region between said source and drain by an insulating layer;
- a high potential detecting circuit coupled to said input terminal;
- and
- a potential setting circuit for setting the source of said MOS transistor to an intermediate potential between the high potential and the low potential in response to a detection of a high potential of the externally-applied input signal by said high potential detecting circuit, whereby an electrical stress to said insulation layer of said MOS transistor substantially equals the difference between the high potential and the intermediate potential.
An input-first stage circuit for use in a semiconductor device, comprising:
- an input terminal for receiving an externally-applied input signal, the externally-applied input signal having at least a high potential and a low potential;
- an N-channel MOS transistor having a source, a drain, and a gate coupled to said input terminal and insulated from a channel region between said source and the drain by an insulating layer;
- a P-channel MOS transistor having a source, a drain coupled to the drain of said N-channel MOS transistor, and a gate coupled to said input terminal and insulated from a channel region between the source and the drain by an insulating layer;
- a high potential detecting circuit coupled to said input terminal;
- and
- a potential setting circuit for setting the source of said N-channel MOS transistor and the source of said P-channel MOS transistor to an intermediate potential between the high potential and the low potential in response to a detection of a high potential of the externally-applied input signal by said high potential detecting circuit, whereby an electrical stress to the insulation layers of said N-channel and P-channel MOS transistors substantially equals the difference between the high potentials and the intermediate potential.
Dependencies are inferred from the claim text.