Clock signal selection circuit

A clock signal selection circuit comprising:

• (a) delay means for delaying a switching control signal to produce a switching delayed control signal;
• (b) first selection circuit means for changing its circuit condition between first and second states in response to a present transition of said switching control signal;
• (c) second selection circuit means for changing its circuit condition between third and fourth states in response to said switching control signal and said output of first selection circuit means, said second selection circuit means supplying a second clock signal in said third state, said second selection circuit means inhibiting a transmission of said second clock signal in said fourth state, said first selection circuit means outputting said first clock signal in said first state, said first selection circuit means inhibiting a transmission of said first clock signal in said second state in response to said switching control signal and said output of second selection circuit means;
• (d) third selection circuit means for selectively supplying said present transition of said switching control signal to either of said first or second selection circuit means in accordance with a condition of said delayed control signal which has been determined at a previous transition of said switching control signal;
• and
• (e) gate means for operating and outputting a logic OR of said first and second clock signals from said first and second selection means respectively.

A clock signal selection circuit for selectively outputting first and second clock signals comprising:

• (a) delay means for delaying a switching control signal to produce a switching delayed control signal;
• (b) first selection circuit means including first switch means for changing its circuit condition between first and second states in response to a present transition of said switching control signal;
• (c) second selection circuit means including second switching means for changing its circuit condition between third and fourth states in response to said switching control signal and said output of first selection circuit means, said second selection circuit means supplying said second clock signal in said third state, said second selection circuit means inhibiting transmission of said second clock signal when operated in said fourth state, said first selection circuit means supplying said first clock signal in said first state, said first selection circuit means inhibiting transmission of said first clock signal when operated in said second condition in response to said switching control signal and said output of second selection circuit means;
• and
• (d) third selection circuit means including said first and second switch means for selectively enabling said switching control signal in either of said first or second selection circuit means in accordance with a condition of said delayed control signal which has been determined at a previous transition of said switching control signal.