Back to results
US 5,289,026 AGranted
Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
AssigneeIntel Corporation
InventorTong-Chern Ong
Life of this patent
Estimating the term…
Abstract
An electrically erasable non-volatile EPROM memory device having an asymmetric floating gate with respect to a buried source region and a buried drain region is disclosed. A patterned floating gate member is formed over a portion of the source region and a portion of the drain region producing a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap.
Claims6
An array of electrically erasable non-volatile memory devices comprising:
- a monocrystalline silicon layer including a plurality of buried source regions and a plurality of buried drain regions, said source regions and said drain regions alternating and spaced apart, wherein said drain regions are shared by adjacent ones of said memory devices in said array;
- wherein each of said memory devices comprises:
- field oxide areas over the source region and the drain region;
- a floating gate member overlapping a portion of the source region and a portion of the drain region forming a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap;
- an insulating layer;
- and
- a control gate member.
4 more elements
Dependencies are inferred from the claim text.