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US 5,289,021 AGranted
Basic cell architecture for mask programmable gate array with 3 or more size transistors
AssigneeSiArc
InventorAbbas El Gamal
Life of this patent
Estimating the term…
Abstract
A highly efficient CMOS cell structure for use in a metal mask programmable gate array, such as a sea-of-gates type gate array, is disclosed herein. In a basic cell, in accordance with one embodiment of the invention, three or more sizes of N-channel transistors and three or more sizes of P-channel transistors are used. The larger size transistors are incorporated in a drive section of a cell, while the smaller size transistors are incorporated in each compute section of a cell. The particular transistors in the compute and drive sections and the arrangements of the compute and drive sections provide a highly efficient use of silicon real estate while enabling the formation of a wide variety of macrocells to be formed.
Claims21
A basic cell in a mask programmable gate array, said basic cell comprising:
- three sizes of N-channel transistors, where size corresponds to channel width;
- and
- three sizes of P-channel transistors, where size corresponds to channel width,
- gates of certain ones of said N-channel transistors and P-channel transistors being isolated from gates of certain other ones of said N-channel transistors and P-channel transistors within said basic cell,
- wherein said basic cell is one of a plurality of basic cells wholly located within an interior of said gate array.
2 more elements
A basic cell in a mask programmable gate array, said basic cell comprising:
- one or more substantially rectangular compute sections, each of said compute sections being identical, each of said compute sections containing MOS transistors for being connected to other transistors;
- and
- one or more substantially rectangular drive sections, each of said drive sections being identical to one another, said one or more drive sections comprising MOS transistors substantially larger than any MOS transistors in said one or more compute sections, said MOS transistors in said drive sections for being connected to other transistors,
- gates of certain ones of said MOS transistors in said basic cell being isolated from gates of certain other ones of said MOS transistors in said basic cell,
- wherein said basic cell is one of a plurality of basic cells wholly located within an interior of said gate array.
2 more elements
A basic cell in a mask programmable gate array, said cell comprising:
- one or more substantially rectangular compute sections and one or more drive sections, said one or more drive sections comprising one or more transistors which are different than transistors in said one or more compute sections, said one or more transistors in said drive sections for being connected to other transistors, each compute section comprising:
- one or more small size N-channel transistors;
- one or more medium size N-channel transistors;
- one or more small size P-channel transistors;
- and
- one or more medium size P-channel transistors,
- said small size N-channel and P-channel transistors having narrower channel widths than said medium size N-channel and P-channel transistors, respectively,
- gates of certain ones of said small size N-channel transistors being isolated from gates of certain ones of said medium size N-channel transistors,
- wherein said basic cell is one of a plurality of basic cells wholly located within an interior of said gate array.
6 more elements
A basic cell in a mask programmable gate array, said cell comprising one or more compute sections, a compute section comprising:
- one or more small size P-channel transistors;
- one or more medium size P-channel transistors;
- one or more small size N-channel transistors;
- and
- one or more medium size N-channel transistors,
- said medium size P-channel transistors having a channel width at least approximately twice the channel width of said small size P-channel transistors, said medium size N-channel transistors having a channel width at least approximately twice the channel width of said small size N-channel transistors, and said small size P-channel transistors having a channel width smaller than said small size N-channel transistors,
- gates of one of said small size P-channel transistors, one of said medium size P-channel transistors, and one of said medium size N-channel transistors being connected in common by polysilicon,
- gates of said small size N-channel transistors being isolated from gates of said small and medium size P-channel transistors and from gates of said medium size N-channel transistors,
- wherein said basic cell is one of a plurality of basic cells wholly located within an interior of said gate array.
6 more elements
An ASIC containing a gate array comprising a plurality of cells, each of said cells comprising:
- three sizes of N-channel transistors, where size corresponds to channel width;
- and
- three sizes of P-channel transistors, where size corresponds to channel width,
- gates of certain ones of said N-channel transistors and P-channel transistors being isolated from gates of certain other ones of said N-channel transistors and P-channel transistors within said basic cell,
- wherein said cells are one of a plurality of cells wholly located within an interior of said gate array.
2 more elements
An ASIC containing a gate array comprising a plurality of cells, each of said cells comprising:
- one or more substantially rectangular compute sections and one or more drive sections, said one or more drive sections comprising one or more transistors which are different than transistors in said one or more compute sections, said one or more transistors in said drive sections for being connected to other transistors, each compute section comprising:
- one or more small size N-channel transistors;
- one or more medium size N-channel transistors;
- one or more small size P-channel transistors;
- and
- one or more medium size P-channel transistors,
- said small size N-channel and P-channel transistors having narrower channel widths than said medium size N-channel and P-channel transistors, respectively,
- gates of certain ones of small size N-channel transistors being isolated from gates of certain ones of said medium size N-channel transistors,
- wherein said cells are one of a plurality of cells wholly located within an interior of said gate array.
6 more elements
An ASIC containing a gate array comprising a plurality of cells, each of said cells comprising one or more compute sections, a compute section comprising:
- one or more small size P-channel transistors;
- one or more medium size P-channel transistors;
- one or more small size N-channel transistors;
- and
- one or more medium size N-channel transistors,
- said medium size P-channel transistors having a channel width at least approximately twice the channel width of said small size P-channel transistors, said medium size N-channel transistors having a channel width at least approximately twice the channel width of said small size N-channel transistors, and said small size P-channel transistors having a channel width smaller than said small size N-channel transistors,
- gates of one of said small size P-channel transistors, one of said medium size P-channel transistors, and one of said medium size N-channel transistors being connected in common by polysilicon,
- gates of said small size N-channel transistors being isolated from gates of said small and medium size P-channel transistors and from gates of said medium size N-channel transistors,
- wherein said cells are located within an interior of said gate array.
6 more elements
A basic cell in a mask programmable gate array, said basic cell comprising:
- one or more substantially rectangular compute sections, each of said compute sections being identical, each of said compute sections containing MOS transistors for being connected to other transistors;
- and
- one or more substantially rectangular drive sections, each of said drive sections being identical to one another, said one ore more drive sections comprising MOS transistors substantially larger than any MOS transistors in said one or more compute sections, said MOS transistors in said drive sections for being connected to other transistors,
- wherein said basic cell is located within an interior of said gate array,
- wherein said one or more substantially rectangular compute sections comprises these compute sections, and said one or more substantially rectangular drive sections comprises one drive section.
2 more elements
Dependencies are inferred from the claim text.