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US 5,289,015 AGranted
Planar fet-seed integrated circuits
AssigneeAT&T Bell Laboratories
InventorsLeo M. F. Chirovsky, Lucian A. D'Asaro, Shin-Shem Pei, Ted K. Woodward
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Abstract
FETs and quantum well diodes are combined on the same semi-insulating substrate, while providing the FETs with protection from spurious voltages. A deeply buried P region in the semi-insulating substrate is partitioned by a high resistivity proton implanted region, to provide both the P region of the quantum well diode and an isolating buried P layer for the FETs.
Claims7
A semiconductor integrated circuit of the type comprising:
- a) a quantum well reflecting stack, b) a buried p-layer of semiconductor overlying said reflector stack, c) a quantum well intrinsic region overlying said p-layer, d) an n-layer of semiconductor overlying said quantum well intrinsic region;
- e) an n-channel field effect transistor comprising a source, a gated n-channel and a drain overlying said quantum well intrinsic region and said buried p-layer;
- and f) a PIN quantum well diode comprised of portions said buried p-layer, said quantum well intrinsic region, and said n-layer,
- CHARACTERIZED IN THAT:
- said buried p-layer is partitioned by a proton implanation region to separate the portion of said p-layer underlying said FET from the portion comprising the p-layer of said diode said proton implantion region being of high resistivity and containing crystal damage.
2 more elements
Dependencies are inferred from the claim text.