Method of manufacture multichip module substrate

A method of forming a multichip module substrate comprising the steps of:

• selecting a planar platform having opposed mutually parallel surfaces;
• forming first via sites on a first of said surfaces of said platform;
• plating in said via sites to form first vias in said via sites to define a first subassembly;
• laminating a first sheet of filled fluoropolymeric composite material onto said first subassembly to define a laminated first subassembly;
• planarizing said laminated first subassembly to expose selected ones of said first vias and to define a first planarized surface;
• depositing a first thin metallized seed layer on said first planarized surface;
• forming "y" circuit line sites and second via sites on said first seed layer;
• plating "y" circuit lines and second vias in said "y" circuit line sites and said second via sites, respectively;
• selectively flash etching said first seed layer to define a second subassembly;
• laminating a second sheet of filled fluoropolymeric composite material onto said second subassembly;
• planarizing said laminated second subassembly to expose selected ones of said second vias and define a second planarized surface;
• depositing a second thin metallized seed layer on said second planarized surface;
• forming "x" circuit line sites and third via sites on said second seed layer;
• plating "x" circuit lines and third vias in said "x" circuit line sites and said third via sites, respectively;
• selectively flash etching said second seed layer to define a third subassembly;
• laminating a third sheet of filled fluoropolymeric composite material onto said third subassembly;
• planarizing said laminated third subassembly to expose selected ones of said third vias and define a third planarized surface;
• depositing a third thin metallized seed layer on said third planarized surface;
• forming voltage plane sites and fourth via sites on said third seed layer;
• plating a voltage plane on said third seed layer and plating fourth vias in said fourth via sites;
• selectively flash etching said third seed layer to define a fourth subassembly;
• providing a cover layer on said fourth subassembly;
• planarizing said covered fourth subassembly to expose selected ones of said fourth vias on a fourth planarized surface;
• depositing a fourth thin metallized seed layer on said fourth planarized surface;
• forming pad sites on said fourth seed layer;
• plating pads in said pad sites;
• and
• selectively flash etching said fourth seed layer.