Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith

Method for providing program code for a real time signal processor means having a memory means, and for concurrently generating memory access code for use by a host processor means so that said host processor means can change the contents of the memory of said signal processor means, wherein object code for said signal processor means and said host processor means are separately compiled, and said signal processor means and said host processor means each include means for interfacing with each other, said method comprising:

• describing and representing a processing task for said signal processor means in a block diagram with a plurality of high level signal processing functional block means and a plurality of connections between said high level signal processing functional block means, each functional block means having a name, at least one of said functional block means having a parameter, and at least one of said functional block means having an indication of being accessible by the host processor means;
• providing a signal processor cell library means containing a plurality of source code blocks, each source code block representing at least a portion of a corresponding high level signal processing functional block means, at least one of said source code blocks containing a named variable for receiving a value for said parameter;
• and
• analyzing said block digram in order to obtain needed code blocks from said signal processor cell library means for implementing said block diagram;
• associating said named variable with said parameter, and
• compiling said code blocks to provide program code and data code for the memory means of the signal processing means, and a correspondence table associating at least one signal processor memory location with said named cell variable,
• providing said correspondence table or a translation thereof for compilation as object code for said host processor means, wherein said correspondence table permits said host processor means to change a parameter value stored as a variable in said memory of said signal processor means.

An apparatus for coupling a host processor and a programmable signal processor having a memory for storing a program and data so that the host processor has intelligent access to the signal processor memory, said apparatus comprising:

• a) high level programming means for defining signal processor functions, said programming means including means for symbolically indicating host processor access to signal processor functions;
• b) signal processor program compiling means coupled to said programming means for generating signal processor program code which causes said signal processor to implement said signal processor functions and for generating memory access code for the host processor, said memory access code including a correspondence table correlating symbolic indications indicated in said programming means with memory addresses in the signal processor memory;
• c) host processor compiling means for generating host processor program code including reference to at least one of said memory addresses in said correspondence table, said host processor compiling means including means for receiving at least a portion of said memory access code;
• and
• d) interface means coupling the host processor and the signal processor memory,
• wherein said host processor program code causes the host processor to access the signal processor memory according to said symbolic indications indicated in said programming means.