Memory system using linear array wafer scale integration architecture

A wafer scale integrated memory system formed on a semiconductor wafer, the memory system including a plurality of memory cells, each of the memory cells comprising:

• connection means for selectively establishing a communication path for data and instructions between a one of the plurality of memory cells and an adjacent one of the memory cells formed on the semiconductor wafer;
• memory means for storing data;
• select means coupled to the connection means for placing the one memory cell in a first state in response to first ones of the instructions;
• circuit means coupling the memory means to the connection means and to the select means for responding, when the one memory cell is in the first state, to second ones of the instructions to access the memory means for storing or retrieving data;
• and
• means for communicating data between the memory means and the connection means.

The memory system constructed from a wafer scale integration of a plurality of memory cells formed on a semiconductor wafer, each of the memory cells comprising:

• N boundaries forming a periphery of the memory cell, each boundary separating the memory cell from a neighbor memory cell formed on the semiconductor wafer adjacent such boundary, each boundary having associated therewith input and output bus means for communicating data and instruction signals, including memory instruction signals, between the neighbor memory cell and the memory cell;
• logic means, including memory means, for storing data in, and accessing data from, the memory means in response to the memory instruction signals;
• connection means associated with each of the N boundaries for selectively communicating data between the memory cell and the neighbor memory cell adjacent such boundary;
• circuit means coupled to the connection means for establishing a data path across at least one of the N boundaries for communicating the data and instruction signals;
• and
• means for selecting predetermined ones of the memory cells for response to the memory instruction signals.

A digital system formed on an integrated circuit wafer, the system including a plurality integrated circuit cells, each of the integrated circuit cells comprising:

• a plurality of boundaries circumscribing the cell, each of the boundaries having a neighbor cell formed on the integrated circuit wafer adjacent such boundary;
• selection means for each boundary to establish a communication path for receiving information from the neighbor cell formed adjacent one or more of the boundaries;
• means coupled to the selection means for each boundary for generating an open signal to cause the selection means to establish the information communication path with the neighbor cell adjacent at least one of the boundaries;
• logic means coupled to the selection means for receiving the information and for performing a digital operation;
• and
• first circuit means for placing the cell in a first state for communicating information between a first neighbor cell adjacent one of the plurality of boundaries and a second neighbor cell adjacent a second of the plurality of boundaries, the first circuit means including second circuit means for placing the cell in a second state responsive to the information from the neighbor cell to perform the digital operation.

A memory system formed by a plurality of memory cells formed on a semiconductor wafer, each of the memory cells comprising:

• N boundaries forming a periphery of the memory cell, each boundary separating the memory cell from a neighbor memory cell formed on the semiconductor wafer adjacent such boundary, each boundary having associated therewith input and output bus means for communicating data and instructions signals, including memory instruction signals, between the neighbor memory cell and the memory cell;
• logic means, including memory means, for storing and accessing data in the memory means in response to memory instructions;
• a plurality of connection means each associated with a corresponding one of the N boundaries for selectively establishing a communication path between the memory cell and the neighbor memory cell adjacent such boundary;
• circuit means coupled to the connection means for selecting at least one of the plurality of connection means to establish the corresponding communication path across at least one of the N boundaries for communicating the data and instruction signals;
• and
• means responsive to certain of the instructions for placing the memory cell in a first state responsive to the memory instructions.