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US 5,287,305 AGranted
Memory device including two-valued/n-valued conversion unit
AssigneeSharp Kabushiki Kaisha
InventorYukihiro Yoshida
Life of this patent
Estimating the term…
Abstract
A memory device comprises a memory cell array including a plurality of memory cells for storing n-valued data, an unit for converting a binary logic data applied thereto into an n-valued logic data when the binary logic data is written into the memory cell array, and an unit for converting an n-valued logic data into a binary logic data when the n-valued logic data is read out from the memory cell array.
Claims35
A memory device comprising:
- a memory cell array including a plurality of memory cells each for storing an n-valued (n is an integer of 3 or larger) digital data;
- means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array;
- and
- means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array.
1 more element
A memory device comprising:
- a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is integer of 3 or larger) datum;
- means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array;
- means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array;
- and
- means for decoding an n-valued logic address applied thereto and for outputting a signal decoded from the n-valued logic address to said memory cell array.
2 more elements
A memory device comprising:
- a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is an integer of 3 or larger) data;
- means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array;
- and
- means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array,
- said means for converting a binary digital data into an n-valued digital data and said means for converting an n-valued digital data into a binary digital data being composed of a bidirectional n-valued/binary data conversion circuit and a bidirectional amplifier coupled between said memory cell array and said bidirectional n-valued/binary data conversion circuits.
2 more elements
Dependencies are inferred from the claim text.