Parallel processing architecture of run-length codes

In an image processing system, an apparatus for separating run-start row addresses and run-end row addresses of black runs in a row of image data, the image data stored in system memories being loaded in by unit of N bit words with control of a central processing unit of a computer wherein N is an integer relating to a storage unit of a computer, said apparatus comprising:

• a pointer for indicating a word start address of a word of image data bits under processing;
• detection means for receiving image data bits of said word and for detecting a presence of a run-start bit and a presence of a run-end bit in said word in parallel;
• means for generating from a first signal in response to detection of the presence of a run-start bit and for generating a second signal in response to detection of the presence of a run-end bit so as to generate said first and said second signals simultaneously;
• a run-start level generator for receiving said image data bits of said word under processing and being activated in response to generation of said first signal for generating run-start levels therefrom, by designating each of the run-start bits in said word as a first binary level and each of the other bits in the word as a second binary level;
• a run-end level generator for receiving said image data bits of said word under processing and being activated in response to generation of said second signal for generating run-end levels therefrom by designating each of the run-end bits in the word as a first binary level and each of the other bits in the word as a second binary level;
• a first and a second trap circuit connected to said run-start level generator and said run-end level generator respectively for converting the run-start levels and the run-end levels to a plurality of trapped run-start word position pulses and a plurality of trapped run-end word position pulses;
• a first and a second encoder connected to the first and the second trap circuits respectively for encoding the plurality of trapped run-start word position pulses and the plurality of trapped run-end word position pulses into serial run-start word addresses and serial run-end word addresses;
• a first and a second adding circuit connected to the first and second encoders respectively for receiving the serial run-start word addresses and the serial run-end word addresses and also connected to said pointer for receiving said word start address, the first and second adding circuits adding the word start address to the serial run-start word addresses and to the serial run-end word addresses respectively to derive serial run-start row addresses and serial run-end row addresses;
• first and second memory means for storing said serial run-start row addresses and serial run-end row addresses respectively so that a central processing unit in said image processing system can access said serial run-start addresses and said serial run-end addresses for further image processing.

A run-length code processing method of generating in parallel run-start row addresses and run-end row addresses of all black runs in a row of digitized image data, the image data being loaded in by units of words from a central processing unit (CPU), the method comprising the steps of:

• (a) detecting in parallel run-start and run-end bits of all the black runs in at least one of the words;
• (b) converting the detected run-start and run-end bits respectively into run-start and run-end addresses in a row of the image data;
• (c) storing the run-start and run-end addresses in two pipelines of first-in-first-out registers;
• (d) effecting steps (a) and (b) without intervention from the CPU and effecting step (c) so as to enable access by the CPU for further image processing;
• and
• acquiring a crossing count during step (b), the crossing count being a total number of change times from white to black information in the digitized image data and being indicative of a total number of the black runs.

A run-length code processing method of generating in parallel run-start row addresses and run-end row addresses of all black runs in a row of digitized image data, the image data being loaded in by units of words from a central processing unit (CPU), the method comprising the steps of:

• (a) detecting in parallel run-start and run-end bits of all the black runs in at least one of the words;
• (b) converting the detected run-start and run-end bits respectively into run-start and run-end addresses in a row of the image data;
• (c) storing the run-start and run-end addresses in two pipelines of first-in-first-out registers;
• (d) effecting steps (a) and (b) without intervention from the CPU and effecting step (c) so as to enable access by the CPU for further image processing;
• detecting a condition in which there is an absence of a run start bit and a run end bit in the one word, the run start bit being a bit whose value is one where a value of an immediately preceding bit is zero, the run end bit being a bit whose value is zero where a value of an immediately preceding bit is one;
• and
• informing the CPU in response to the detection of the condition to load in the image data of the next word.

A run-length code processing apparatus useful for generating in parallel run-start row addresses and run-end row addresses of all black runs in a row of digitized image data, the image data being loaded in by units of words to be processed from a central processing unit (CPU), the apparatus comprising:

• means for detecting in parallel run-start and run-end bits of all the black runs in at least one of the words to be processed;
• means for converting the detected run-start and run-end bits respectively into run-start and run-end addresses in a row of the image data;
• means for storing the run-start and run-end addresses in two pipelines of first-in-first-out registers;
• means for effecting operation of said detecting means and said converting means without intervention from the CPU;
• means for enabling access of said storing means by the CPU for further image processing;
• and
• acquiring a crossing count in response to operation of said converting means, the crossing count being a total number of change times from white to black information in the digitized image data and being indicative of a total number of the black runs.

A run-length code processing apparatus useful for generating in parallel run-start row addresses and run-end row addresses of all black runs in a row of digitized image data, the image data being loaded in by units of words to be processed from a central processing unit (CPU), the apparatus comprising:

• means for detecting in parallel run-start and run-end bits of all the black runs in at least one of the words to be processed;
• means for converting the detected run-start and run-end bits respectively into run-start and run-end addresses in a row of the image data;
• means for storing the run-start and run-end addresses in two pipelines of first-in-first-out registers;
• means for effecting operation of said detecting means and said converting means without intervention from the CPU;
• means for enabling access of said storing means by the CPU for further image processing;
• means for detecting a condition in which there is an absence of a run start bit and a run end bit in the one word, the run start bit being a bit whose value is one where a value of an immediately preceding bit is zero, the run end bit being a bit whose value is zero where a value of an immediately preceding bit is one;
• and
• means for informing the CPU in response to the detection of the condition to load in the image data of the next word.