US 5,287,108 A · Multistep analog-to-digital converter with successive approximation register circuit for least significant bit resolution

Abstract

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value.

Claims10

Dependent claims

An analog-to-digital converter, said analog-to-digital converter generating an X-bit digital output signal representing an input signal's analog voltage, where X is an integer greater than six, said analog-to-digital converter comprising:

an input circuit that receives an input signal having an input voltage;
a resistor ladder circuit that generates a set of reference voltages;
initial conversion means for comparing said input voltage with at least a subset of said reference voltages to produce a first set of comparison signals;
a digital encoder, coupled to said initial conversion means, that encodes said first set of comparison signals to generate a first digital conversion value having X-J bits and a resolution of 2.sup.J LSB, where J.gtoreq.1 and 1 LSB is said X-bit digital output signal's resolution;
a multiplicity of parallel switched capacitor circuits that simultaneously generate a set of comparison voltages stepped in 1 LSB increments;
final conversion means for simultaneously comparing a first voltage, corresponding to said input voltage, with said set of comparison voltages to produce a second set of comparison signals;
said digital encoder including means for encoding said second set of comparison signals to generate a second digital conversion value having Y bits, wherein Y-J>1, whereby Y-J additional bits are generated;
correction means for combining said Y-J additional bits with said first digital conversion value to generate a corrected first digital conversion value;
and
output means for combining said corrected first digital conversion value and J bits of said second digital conversion value to produce said X-bit digital output signal.

7 more elements

an input circuit that receives an input signal having an input voltage;
a resistor ladder circuit that generates a set of reference voltages;
initial conversion means for comparing said input voltage with at least a subset of said reference voltages to produce a first set of comparison signals;
a digital encoder, coupled to said initial conversion means, that encodes said first set of comparison signals to generate a first digital conversion value having X-J bits and a resolution of 2.sup.J LSB, where J.gtoreq.1 and 1 LSB is said X-bit digital output signal's resolution;
means for generating a residual voltage corresponding to a selected one of said set of reference voltages, corresponding to said first digital conversion value, minus said input voltage;
a multiplicity of parallel switched capacitor circuits that simultaneously generate a set of comparison voltages;
said set of comparison voltages stepped in 1 LSB increments with respect to said residual voltage;
final conversion means for simultaneously comparing said residual voltage with said set of comparison voltages to produce a second set of comparison signals;
said digital encoder including means for encoding said second set of comparison signals to generate a second digital conversion value having Y bits, wherein Y-J>1, whereby at least two additional bits are generated;
correction means for combining said at least two additional bits with said first digital conversion value to generate a corrected first digital conversion value;
and
output means for combining said corrected first digital conversion value and J bits of said second digital conversion value to produce said X-bit digital output signal.

9 more elements

A method of metering an analog input signal's voltage so as to generate an X-bit digital output signal, where X is an integer greater than six, said the steps of the method comprising:

receiving an analog input signal having an input voltage;
comparing said input voltage with a set of reference voltages to produce a first set of comparison signals;
encoding said first set of comparison signals to generate a first digital conversion value having X-J bits and a resolution of 2.sup.J LSB, where J.gtoreq.1 and 1 LSB is said X-bit digital output signal's resolution;
generating a residual voltage corresponding to a selected one of said set of reference voltages, corresponding to said first digital conversion value, minus said input voltage;
operating a multiplicity of parallel switched capacitor circuits to simultaneously generate a set of comparison voltages stepped in 1 LSB increments with respect to said residual voltage;
simultaneously comparing a said residual voltage with each of said set of comparison voltages to produce a second set of comparison signals;
encoding said second set of comparison signals to generate a second digital conversion value having Y bits, wherein Y-J>1, whereby at least two additional bits are generated;
correcting said first digital conversion value according to said at least two additional bits;
and
combining said corrected first digital conversion value and said second digital conversion value to produce said X-bit digital output signal.

7 more elements

an input circuit that receives an input signal having an input voltage;
a resistor ladder circuit that generates a set of reference voltages;
a voltage estimator for comparing said input voltage with a first subset of said reference voltages to produce a digital estimate value;
a flash converter for comparing said input voltage with a second subset of said reference voltages to produce a first set of comparison signals;
and
a digital encoder, coupled to said voltage estimator and said initial conversion means, that encodes said first set of comparison signals, corrects said digital estimate value based on said encoded comparison signals and combines said corrected digital estimate value with said encoded comparison signals to generate a first digital conversion value having X-J bits and a resolution of 2.sup.J LSB, where J.gtoreq.1 and 1 LSB is said X-bit digital output signal's resolution;
a multiplicity of parallel switched capacitor circuits that simultaneously generate a set of comparison voltages stepped in 1 LSB increments;
final conversion means for simultaneously comparing a first voltage, corresponding to said input voltage, with said set of comparison voltages to produce a second set of comparison signals;
said digital encoder including means for encoding said second set of comparison signals to generate a second digital conversion value having Y bits, wherein Y>J, whereby Y-J additional bits are generated;
correction means for combining said Y-J additional bits with said first digital conversion value to generate a corrected first digital conversion value;
and
output means for combining said corrected first digital conversion value and J bits of said second digital conversion value to produce said X-bit digital output signal.

9 more elements

Dependencies are inferred from the claim text.

Multistep analog-to-digital converter with successive approximation register circuit for least significant bit resolution

Life of this patent

Multistep analog-to-digital converter with successive approximation register circuit for least significant bit resolution

Life of this patent

Abstract

Claims10