Amplifier with high common mode rejection

The combination comprising,

• a differential amplifier having first and second differentially connected transistors;
• each transistor having first and second electrodes defining the ends of a main conduction path and a control electrode, the conductivity of each transistor being a function of the potential applied between its control and first electrodes;
• means for applying voltages to the control electrodes of the first and second transistors;
• means connecting the first electrodes of said first and second transistors to a common node;
• a first controllable current source connected between said common node and a first power terminal for the application thereto of an operating potential;
• first and second current mirror amplifiers (CMA), each CMA having an input and an output.
• means respectively connecting the inputs of the first and second CMAs to the second electrodes of the first and second transistors;
• a summing node;
• means connecting the outputs of the first and second CMAs to said summing node for supplying first and second currents of the same one polarity to said summing nodes;
• a bias current generating means coupled to said summing node for supplying a bias current thereto of opposite polarity to that of said first and second currents of said first and second CMAs;
• and
• means coupled between said summing node and said first controllable current source responsive to the voltage at said summing node for maintaining the current of said first controllable current source relatively constant in response to like voltages applied to the control electrodes of said first and second transistors.

A differential amplifier comprising:

• a plurality of transistors, each transistor having first and second electrodes defining the ends of a main conduction path and a control electrode, and wherein the conductivity of the main conduction path of each transistor is a function of the potential applied between its control and first electrodes;
• first and second input terminals for the application there between of an input signal;
• means connecting the control electrode of a first one of said plurality of transistors to said first input terminal and the control electrode of a second one of said plurality of transistors to said second input terminal;
• a first controllable, relatively constant current source connected between the first electrodes of said first and second transistors and a first power terminal for supplying a quiescent current to said first and second transistors;
• a third transistor having its second and control electrodes connected to the second electrode of said first transistor at a first output node;
• a fourth transistor having its second and control electrodes connected to the second electrode of said second transistor at a second output node;
• means connecting the first electrodes of said third and fourth transistor to a second power terminal;
• a fifth transistor having its control electrode connected to said first output node and a sixth transistor having its control electrode connected to said second output node;
• a summing node;
• means connecting the second electrodes of said fifth and sixth transistors to said summing node and their first electrodes to said second power terminal;
• means for supplying a bias current to said summing node;
• a seventh transistor having its control electrode connected to said summing node and its first electrode to said second power terminal;
• and
• means coupled between the second electrode of said seventh transistor and the first controllable current source for controlling the current through said first controllable current source as a function of the conductivity of said seventh transistor.