US 5,285,403 AGranted

Arithmetic processing module to be associated with a microprocessor central processing unit

AssigneeU.S. Philips Corporation

InventorsJean-Jacques Quisquater, Jean-Pierre Bournas, Dominique De Waleffe

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Abstract

A processing module for performing an operation of the type B=a.X+T in which B, X and T are high value integers, and a is an operand having a format restricted to m bits, in sequences constituted from computing steps consisting in combining the operand a with operands x.sub.i and t.sub.i, of restricted format, extracted from the data X and T, at the rank of significance i and in storing a partial result b.sub.i of the same significance rank, this processing module including a static multiplier and two adders and a resistor for storing and recycling the most significant portion of a previous computing step. The processing module includes k inputs for operands a (l . . . k) of successive ranks, for successively applying, in work cycles k steps the said operands a (l . . . k) to one of the inputs of the multiplier, registers and multipliers enabling a delay of k computing steps in the most significant portion of the result at the output of a second adder and of (k-1) computing steps in the least significant portion of the same result, respectively in the first step and in the other steps of each cycle.

Claims20

Dependent claims

An arithmetic processing module for use in a microprocessor for calculating in k cycles a product B of binary operands a, X, T, according to B=aX+T, based on an n-bit format, each of said binary operands a, X, T having a format of greater than n-bits, each bit of each of said binary operands having a significance level relative to every other of said bits, said operand a separated into k portions, each of said k portions having said n-bit format, said module comprising:

data transfer means for communicating said product and operands within said module according to said n-bit format;
storage means having k sections for storing said operand a, each section of said storage means having said n-bit format;
selection means coupled to said storage means for cyclically selecting one of said k portions of operand a during each of said k cycles, said selection means cyclically selecting said portion of operand a according to increasing significance levels;
multiplier means for receiving in each cycle said portion of operand a selected by said selection means and a portion of operand X having said n-bit format and having the same significance level as said portion of operand a and outputting a product of said portion of said operand X and said portion of operand a;
adder means for adding a portion of operand T and said output of said multiplier means and outputting as a first output and a second output portions of said product B, said first output having a higher significance level than said second output;
recycling means for retaining said first output for k cycles and for retaining said second output for k-1 cycles and then retrocoupling said first output and said second output to said adder means in place of said portion of said operand T.

3 more elements

An arithmetic processing module for use in a microprocessor for calculating in p cycles a product B of binary operands, a, X, T, according to B=aX+T, based on an n-bit format, each of said binary operands a, X, T having a format of greater than n-bits, each bit of each of said binary operands having a significance level relative to every other of said bits, said operand a separated into p portions, each of said p portions having said n-bit format, said module comprising:

data transfer means for communicating said product and operands within said module according to said n-bit format;
storage means having k sections for storing said p portions of said operand a, each section of said storage means having said n-bit format;
selection means coupled to said storage means for cyclically selecting one of said k portions of operand a during each of said p cycles, said selection means cyclically selecting said portion of operand a according to increasing significance levels;
multiplier means for receiving in each cycle said portion of operand a selected by said selection means and a portion of operand X having said n-bit format and having the same significance level as said portion of operand a and outputting a product of said portion of said operand X and said portion of operand a;
adder means for adding a portion of operand T and said output of said multiplier means and outputting as a first output and a second output portions of said product B, said first output having a higher significance level than said second output;
recycling means for retaining said first output for p cycles and for retaining said second output for p-1 cycles and then retrocoupling said first output and said second output to said adder means in place of said portion of said operand T.

3 more elements

Dependencies are inferred from the claim text.