Method of multi-level storage in DRAM
AssigneeMosaid Technologies Incorporated
InventorPeter B. Gillingham
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Abstract
A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.
Claims9
A method of processing data having one of four voltage levels stored in a DRAM cell comprising:
- (a) sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of said four levels,
- (b) setting the voltage on a reference line higher than the lowest and lower than the next highest of said four levels in the event the data voltage is below said midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of said four levels in the event the data voltage is above said midway voltage level, and
- (c) sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.
A method of processing data having one of plural levels stored in a DRAM cell capacitor comprising:
- (a) dumping the charge of the cell capacitor on a first conductor of a pair of conductors of a folded bitline,
- (b) maintaining the other conductor of said pair of conductors split into other sub-bitline conductors and charging each of said other sub-bitline conductors to an intermediate voltage,
- (c) splitting said first of said pair of conductors into first sub-bitline conductors,
- (d) sensing one of said sub-bitline conductors to determine whether the charge of said cell has a higher voltage than the intermediate voltage of one of said other sub-bitline conductors and providing a logic level result signal,
- (e) storing said logic level result signal in a dummy cell capacitor,
- (f) setting a charge storage capacitor and all of the sub-bitlines other than a first sub-bitline conductor on which the charges of cell capacitor was dumped, at to a predetermined voltage,
- (g) dumping charge stored in the dummy cell capacitor on said sub-bitlines conductors other than the first sub-bitline conductor to which the charge of the cell capacitor was dumped, and on said charge storage capacitor together, thereby varying the predetermined voltage stored thereon to a degree related to the capacities of said dummy cell capacitor, said charge storage capacitor and said predetermined voltage, to a level above or below the intermediate level,
- (h) isolating the sub-bitlines,
- (i) applying said intermediate voltage to one of said other sub-bitline conductors,
- (j) comparing the cell voltage on one sub-bitline with the voltage on said other sub-bitline carrying said level above or below the intermediate level to obtain a first logic bit, and comparing the voltages carried by the other sub-bitlines to obtain a second logic bit,
- whereby said first and second logic bits are indicative of one of four states corresponding to one of said plural levels stored in the DRAM cell.
Dependencies are inferred from the claim text.