US 5,283,483 A · Slimmer circuit technique

Abstract

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2 Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mbps, and is built in a 1.5.mu./4 GHz BiCMOS technology.

Claims11

Dependent claims

A slimmer circuit for narrowing data pulses comprising:

a. means for receiving a voltage signal having a characteristic;
b. a circuit for forming a bandpass response signal for the voltage signal;
c. a circuit for forming a lowpass response signal for the voltage signal;
d. means for forming a second derivative of the bandpass response signal for forming a second derivative signal;
e. means for amplifying the second derivative signal for forming an amplified signal;
and
f. means for subtracting the amplified signal from the lowpass response signal for forming a difference signal.

4 more elements

A slimmer circuit for narrowing data pulses comprising:

a. a differential amplifier having a positive input, a negative input, a positive output and a negative output;
b. a first capacitor having a first terminal coupled to the positive input;
c. a first current source coupled to the positive input;
d. a second capacitor having a first terminal coupled to the negative input;
e. a second current source coupled to the negative input;
f. a first voltage signal coupled to a second terminal of the first capacitor and to a second terminal of the second capacitor;
g. a first and a second n-channel MOS transistor having a gate coupled to the positive output of the amplifier and a source coupled to a circuit ground;
h. a drain of the first transistor coupled to the positive input of the amplifier;
i. a third and a fourth n-channel MOS transistor having a gate coupled to the negative output of the amplifier and a source coupled to a circuit ground;
j. a drain of the third transistor coupled to the negative input of the amplifier;
k. a differential transconductor having a positive input, a negative input, a positive output and a negative output;
l. a second voltage signal coupled to the positive input and the negative input of the transconductor;
m. a drain of the second transistor coupled to the positive output of the transconductor;
and
n. a drain of the fourth transistor coupled to the negative output of the transconductor.

12 more elements

Dependencies are inferred from the claim text.

Slimmer circuit technique

Life of this patent

Slimmer circuit technique

Life of this patent

Abstract

Claims11