# US 5,282,922 A · Hybrid circuit structures and methods of fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,282,922 A - Document ID: US5282922A - Status: Granted - Kind: A - Application number: 07/850,382 - Filed: 1992-03-11 - Granted: 1994-02-01 - Earliest claimed: 1989-11-16 - Assignees: Polycon Corporation - Inventors: John J. Reche - Web page: https://patentgrep.com/patent/US5282922A ## CPC - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 90/00: Package configurations - Y10S 148/103: Mask, dual function, e.g. diffusion and oxidation - Y10S 148/106: Masks, special - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract Hybrid circuit structures and methods of fabrication particularly suitable for the fabrication of high density multi-layer interconnects utilizing silicon substrates are disclosed. In accordance with the method, a layer of alumina is put down over the silicon substrate, typically having an oxide layer thereover, which layer of alumina acts as a blocking barrier to any subsequent plasma etching process for etching polymer layers thereover during the subsequent high density multilayer interconnect fabrication steps. Various representative high density multi-layer interconnect structures on silicon substrates and methods of forming the same are disclosed, including the inclusion of an adhesion enhancement layer over the layer of alumina to enhance the adhesion of a polymer which would not otherwise adhere well directly to the layer of alumina. ## Claims ### Claim 1 A method of patterning a polymer layer over a silicon substrate comprising the steps of; (a) providing a layer of material resistant to fluorine ion bearing plasma over an entire first surface of the silicon substrate; (b) applying a conductive layer over at least a portion of said resistant material wherein said conductive layer is entirely separated from the silicon substrate by said resistant material; (c) applying a polymer layer to said resistant material wherein said polymer layer is entirely separated from the silicon substrate by said resistant material; and, (d) etching a portion of said polymer layer with a fluorine ion bearing plasma, wherein said resistant material prevents said fluorine ion bearing plasma from etching the silicon substrate. ### Claim 2 (depends on 1) The method of of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is a layer of material selected from the group consisting of aluminum oxide, hafnium oxide and tungsten tri-oxide. ### Claim 3 (depends on 1) The method of of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is provided by sputtering. ### Claim 4 (depends on 1) The method of of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is provided by ion beam deposition. ### Claim 5 (depends on 1) The method of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is provided by heating a sol-gel or organo-metallic in an oxidizing atmosphere. ### Claim 6 (depends on 1) The method of of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is provided by depositing a layer of aluminum over the silicon substrate and oxidizing the same. ### Claim 7 (depends on 1) The method of of claim 1 wherein the layer provided over the first surface of the silicon substrate in step (a) is provided by sputtering a layer of alumina onto the silicon substrate. ### Claim 8 (depends on 1, 2, 3, 4, 5, 6, 7) The method of of any of claims 1, 2, 3, 4, 5, 6 or 7 wherein said conductive layer is a conductive ground plate. ### Claim 9 (depends on 1) The method of of claim 1 further comprising the step of patterning the conductive layer. ### Claim 10 (depends on 1, 2, 3, 4, 5, 6, 7) The method of of claims 1, 2, 3, 4, 5, 6 or 7 further comprising the step of providing an adhesion layer over the layer formed in step (a) prior to forming the conductive layer. ### Claim 11 (depends on 10) The method of of claim 10 wherein the adhesion layer is a layer of silicon oxide. ### Claim 12 A method of patterning a polymer layer over a silicon substrate comprising the steps of; (a) sputtering a layer of alumina over an entire first surface of the silicon substrate; (b) applying a conductive layer over a portion of said layer of alumina; (c) applying a polymer layer over said conductive layer and said layer of alumina wherein said conductive and polymer layers are entirely separated from the silicon substrate by said layer of alumina; and (d) etching a portion of said polymer layer with a fluorine ion bearing plasma, wherein said layer of alumina prevents said fluorine ion bearing plasma from etching the silicon substrate. ### Claim 13 (depends on 12) The method of of claim 12 further comprising the step of patterning the conductive layer. ### Claim 14 (depends on 12, 13) The method of of claims 12 or 13 further comprising the step of providing an adhesion layer over the layer of alumina formed in step (a) prior to forming the conductive layer in step (b). ### Claim 15 (depends on 14) The method of fabricating a high density multichip interconnect of claim 14 wherein the adhesion layer is a layer of silicon oxide.