US 5,282,274 A · Translation of multiple virtual pages upon a TLB miss

Abstract

Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addresses upon the occurrence of a miss in a translation lookaside buffer (TLB). In response to a TLB miss, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses. The virtual and corresponding page frame addresses for this block are then stored within a single TLB entry. Inasmuch as successive virtual page addresses can be constructed through simple incrementation of a starting virtual page address for this block, a TLB entry contains the first virtual page address for the block followed by the separate page frame address, and its associated invalid and page protection bit fields, for each of the contiguous virtual pages in that block. Since segment and block values are the same for all the page frame addresses in each block, these values are only stored once within the corresponding TLB entry for that block.

Claims28

Dependent claims

In a digital computer, a method for use in translating an incoming memory address in a first address space into a corresponding memory address in a second address space comprising the steps of:

translating, in response to a miss in a translation lookaside buffer (TLB), a plurality of successive contiguous page addresses in said first address space into a corresponding plurality of page addresses in said second address space, said plurality of successive contiguous page addresses in said first address space containing a page address of said incoming memory address;
and
storing, in the TLB, said plurality of page addresses in said second address space.

In a digital computer, a method for use in translating an incoming virtual memory address into a corresponding real memory address comprising the steps of:

accessing a translation lookaside buffer (TLB) comprising:
searching the TLB, in response to an incoming virtual page address contained in said incoming virtual memory address, for a TLB entry that contains real page addresses for a block of corresponding contiguous virtual page addresses containing said incoming virtual page address;
generating, in response to said searching step, a TLB miss in the event said TLB entry does not exist in the TLB;
and
determining, in response to said searching step and the existence of said TLB entry, whether one of said real page addresses stored therein and corresponding to said incoming virtual page address is valid;
and if valid, reading said one real page address from said TLB entry as a corresponding translated real page address, otherwise generating a TLB miss;
and
updating the TLB, in response to said TLB miss, comprising:
translating a plurality of successive contiguous virtual page addresses into a corresponding plurality of real page addresses, said plurality of successive contiguous virtual page addresses containing said incoming virtual page address and forming the block of said corresponding contiguous virtual page addresses;
creating a new TLB entry for said block, said new TLB entry containing a first one of said plurality of successive contiguous virtual page addresses and each of said plurality of real page addresses;
and
inserting said new TLB entry into the TLB.

9 more elements

Dependencies are inferred from the claim text.

Translation of multiple virtual pages upon a TLB miss

Life of this patent

Translation of multiple virtual pages upon a TLB miss

Life of this patent

Abstract

Claims28