Multiple register block write method and circuit for video DRAMs

In a memory device having an array of randomly addressable memory registers, blocks of said memory registers being selectable for block writing from a register during a block write cycle, a multiple write register circuit comprising:

• a plurality of write registers;
• a write register decoder connected to the plurality of write registers to address a selected one of the write registers from which a selected block of memory registers is written during a block write cycle;
• and
• first and second address inputs in which the write register decoder is responsive to the first address input during a write register load cycle to address a first write register for loading data to the first write register and wherein the write register decoder is responsive to the second address input during a block write cycle to address a second write register from which data is written in parallel to the selected block of memory registers.

A random access memory integrated circuit comprising:

• a plurality of memory registers, each memory register comprising at least one memory cell, blocks of said memory registers being selectable for block writing;
• an address bus which receives memory register addresses that specify memory registers for reading and writing;
• a data bus which receives memory register data for writing to memory registers;
• and
• a multiple write register circuit having a plurality of individually addressable write registers, each of the write registers being selectively connectable for writing to at least a common one of the selectable blocks of memory registers, the multiple write register circuit writing data from an addressed write register in parallel to a selected block of memory registers during a block write cycle.

A random access memory integrated circuit comprising:

• a plurality of memory registers, each memory register comprising at least one memory cell;
• an address bus which receives memory register addresses that specify memory registers for reading and writing;
• a data bus which receives memory register data for writing to memory registers;
• and
• a multiple write register circuit having a plurality of individually addressable write registers, the multiple write register circuit writing data from an addressed write register in parallel to a selected block of memory registers during a block write cycle, wherein the selected block of memory registers is a row of memory registers from the plurality of memory registers.

A random access memory integrated circuit comprising:

• a plurality of memory registers, each memory register comprising at least one memory cell;
• an address bus which receives memory register addresses that specify memory registers for reading and writing;
• a data bus which receives memory register data for writing to memory registers;
• and
• a multiple write register circuit having a plurality of individually addressable write registers, the multiple write register circuit writing data from an addressed write register in parallel to a selected block of memory registers during a block write cycle;
• and
• the multiple write register circuit comprising a write register decoder which is responsive to a write register address received from the data bus during a block write cycle to address a write register, the multiple write register circuit writing data from the addressed write register to the selected block of memory registers during said block write cycle.

A dynamic random access memory integrated circuit comprising:

• rows and columns of memory registers, each memory register comprising at least one dynamic memory cell;
• a multiplexed address bus which sequentially receives memory register row and column addresses that specify rows and columns of memory registers for reading and writing;
• a data bus which receives memory register data for writing to memory registers;
• said address bus further receiving a memory register base address, said memory register base address specifying a predefined number of consecutively-addressed memory registers within a row for simultaneous writing;
• and
• a multiple write register circuit having a plurality of individually addressable write registers each corresponding in width to the memory registers;
• the multiple write register circuit providing data from an addressed write register to the predefined number of consecutively-addressed memory registers during a block write cycle.

In a random access memory integrated circuit having an array of randomly addressable memory registers, blocks of said memory registers being selectable for block writing from a write register during a block write cycle, a method of performing a block write cycle, comprising:

• storing data in a plurality of write registers, each of the write registers being selectively connectable for writing to a common one of the selectable blocks of said memory registers;
• addressing one of the write registers from among the plurality of write registers;
• and
• writing data from the addressed write register in parallel to a selected block of memory registers.

In a random access memory integrated circuit having a plurality of memory registers, the memory integrated circuit having an address bus for receiving memory register addresses and a data bus for receiving and producing memory register data, a method of writing to a selected block of the memory registers in a block write cycle, comprising:

• receiving a first write register address from the address bus during a write register load cycle;
• storing data in a first write register associated with the first write register address during said write register load cycle;
• receiving a second write register address from the data bus during a block write cycle;
• receiving a memory register base address;
• addressing a second write register associated with the second write register address during said block write cycle;
• addressing a predefined number of consecutively-addressed memory registers including a memory register having the memory register base address during said block write cycle;
• and
• writing data from the second write register in parallel to the predefined number of consecutively-addressed memory registers during said block write cycle.

In a random access memory integrated circuit having an array of randomly addressable memory registers, blocks of said memory registers being selectable for block writing from a write register during a block write cycle, a method of performing a block write cycle, comprising:

• storing data in a plurality of write registers;
• addressing one of the write registers from among the plurality of write registers;
• and
• writing data from the addressed write register in parallel to a selected block of memory registers;
• receiving a memory register base address;
• and
• addressing a predefined number of consecutively-addressed memory registers including a memory register having the memory register base address, the predefined number of consecutively-addressed memory cells constituting the selected block of memory registers.