Semiconductor integrated circuit having self-check and self-repair capabilities

A semiconductor integrated circuit device formed on a single chip for testing a memory cell for defects, comprising:

• an address terminal which is supplied with a first address corresponding to a memory cell to be tested for defects;
• first memory means including a first plurality of word lines, a first plurality of data lines, and a first plurality of memory cells each of which has a selection terminal coupled to a corresponding one of said first plurality of word lines and a data input/output terminal coupled to a corresponding one of said first plurality of data lines;
• second memory means including a second plurality of word lines, a second plurality of data lines, and a second plurality of memory cells each of which has a selection terminal coupled to a corresponding one of said second plurality of word lines, and a data input/output terminal coupled to a corresponding one of said second plurality of data lines, said second plurality of memory cells serving to substitute for defective ones of said first plurality of memory cells of said first memory means;
• address generation means for delivering a second address by which to select one word line from among said first plurality of word lines which are included in said first memory means;
• first selection means for selecting one word line from among said first plurality of word lines which are included in said first memory means;
• second selection means for selecting one word line from among said second plurality of word lines which are included in said second memory means;
• error decision means for reading out data stored in the memory cell corresponding to said second address, the memory cell being coupled to said word line selected by said first selection means, for deciding whether or not said memory cell is defective by comparing the data read out from the memory cell with predetermined data, and for delivering a signal of a result of the decision;
• address storage means for receiving and storing said second address when said error decision means delivers a signal which indicates that said memory cell coupled to said selected word line is defective;
• and
• address decision means for determining whether an address of a memory cell of said first emory means is defective by comparing the first address and the second address stored in said address storage means, so as to decide coincidence/noncoincidence of the first and second addresses, including means for delivering said first address to said second selection means when the first and second addresses have been decided to be coincident by said address decision means, and means for delivering said first address to said first selection means when the first and second addresses have been decided to be noncoincident;
• wherein said address generation means delivers the second address to the first selection means, and wherein the first and second selection means select a word line from the first and second plurality of word lines, respectively, based upon addresses delivered thereto.