Temperature-dependent DRAM refresh circuit
AssigneeMicron Technology, Inc.
InventorsCharles W. Tillinghast, Michael S. Cohen, Thomas W. Voshell
Life of this patent
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Abstract
A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array. The temperature circuit removes the refresh guardbanding on the DRAMS. Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array.
Claims22
A circuit f or setting the refresh rate of a logic component based on the temperature of the component, comprising:
- a) a temperature sensor having an output which reflects the temperature of the logic component;
- b) a plurality of comparators, each comparator having a first input coupled to a voltage divider between a V.sub.cc source and ground, a second input coupled to said temperature sensor output, and an output;
- c) an encoder having at least two binary outputs, said encoder receiving said comparator outputs and encoding said comparator outputs into a binary signal on said binary outputs;
- d) at least two binary weight resistors with at least one binary weight resistor coupled to each of said binary outputs, with each binary weight resistor having a different value such that each of said binary outputs has a different binary weight;
- e) a summing node, said binary weight resistors on said binary outputs interposed between said summing node and said encoder, said summing node having a voltage which reflects said binary signal;
- f) an oscillator coupled with said summing node, said oscillator outputting a timed signal based on said voltage on said summing node;
- and
- g) refresh circuitry which initiates a refresh of the component upon receipt of said timed signal.
A circuit for setting the refresh rate of a logic component based on the temperature of the component, comprising:
- a) a temperature sensor having an output which reflects the temperature of said logic component;
- b) a comparator having a first input coupled to a voltage divider between a V.sub.cc source and ground, a second input coupled to said temperature sensor output, and output, and a feedback loop comprising a first resistor interposed between said comparator output and said second comparator input thereby providing hysteresis to said comparator;
- c) a second resistor interposed between said temperature sensor output and said second comparator input, thereby scaling said second comparator input;
- d) a third resistor interposed between said V.sub.cc source and said first comparator input, thereby scaling said first comparator input and forming a voltage divider;
- e) an oscillator coupled with said comparator output, said oscillator outputting a timed signal based on said output of said comparator;
- and
- f) refresh circuitry which initiates a refresh of the component upon receipt of said timed signal,
- wherein said refresh rate changes when said comparator output switches from a first digital level to a second digital level.
A circuit for setting the refresh rate of a random access memory array based on the temperature of the array, the circuit comprising:
- a) a temperature sensor having an output which reflects the temperature of the memory array;
- b) a plurality of comparators, each comparator having a first input coupled to a voltage divider between a first power source and ground, a second input coupled to said temperature sensor output, and an output;
- c) an encoder having at least two binary outputs, said encoder receiving said comparator outputs and encoding said comparator outputs into a binary signal on said binary outputs;
- d) at least two binary weight resistors with at least one binary weight resistor coupled to each of said binary outputs, with each binary weight resistor having a different value such that each of said binary outputs has a different binary weight;
- e) a summing node, said binary weight resistors on said binary outputs interposed between said summing node and said encoder, said summing node having a voltage which reflects said binary signal;
- f) an oscillator coupled with said summing node, said oscillator outputting a timed signal based on said voltage on said summing node;
- and
- g) refresh circuitry which initiates a refresh of the memory array upon receipt of said timed signal.
Dependencies are inferred from the claim text.