Voltage compensating CMOS input buffer

A voltage compensating CMOS input buffer circuit to stabilize input level trip points, said circuit comprising:

• first, second and third potential sources;
• a voltage adjusting circuit providing a voltage adjusting output node, said voltage adjusting circuit coupled between said first and third potential sources;
• a voltage compensating circuit providing a voltage compensating drive node, said voltage compensating circuit coupled to said voltage adjusting output node and said second potential source;
• and
• an input buffer circuit having an input node and an output node, said input buffer coupled between said voltage compensating drive node and said third potential source.

A voltage compensating CMOS input buffer circuit to stabilize input level trip points, said circuit comprising:

• first, second and third potential sources;
• a voltage adjusting circuit providing a voltage adjusting output node, wherein said voltage adjusting circuit comprises:
• first and second PMOS transistors and an NMOS transistor, each transistor having an gate terminal, a source terminal and a drain terminal, said first PMOS transistor having its source terminal coupled to said first potential source and its gate and drain terminals coupled to said second PMOS transistor's source terminal, said second PMOS transistor having its gate and drain terminals coupled to said NMOS transistor's drain terminal thereby forming said voltage adjusting output node, said NMOS transistor's gate terminal coupled to said first potential source and its source terminal coupled to said third potential source;
• a voltage compensating circuit providing a voltage compensating drive node, wherein said voltage compensating circuit comprises:
• a PMOS transistor having a gate terminal, a source terminal and a drain terminal, said PMOS transistor's gate terminal coupled to said voltage adjusting output node, its source terminal coupled to said second potential source and its drain terminal coupled to said voltage compensating drive node;
• and
• an input buffer circuit having an input node and an output node, wherein said input buffer circuit comprises:
• first and second PMOS transistor and first and second NMOS transistors, each transistor having a gate terminal, a source terminal and a drain terminal, said gate terminals of all four transistors are coupled together thereby forming an input node, said first PMOS transistor's source terminal coupled to said voltage compensating drive node and its drain terminal coupled to said second PMOS transistor's source terminal, said second PMOS transistor's drain terminal coupled to said first NMOS transistor's drain terminal thereby forming said output node, said first transistor's source terminal coupled to said second NMOS transistor's drain terminal and said second NMOS transistor's source terminal coupled to said third potential source.