Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

A process for doping a layer of polycrystalline silicon with a pair of dopant materials to form a pair of gates during the formation of a semiconductor device, said process comprising the following steps:

• a) doping a first portion of a semiconductor substrate with a first material having a first type conductivity;
• b) doping a second portion of said substrate with a second material having a second type conductivity;
• c) forming a layer of dielectric over said substrate;
• d) forming a layer of polycrystalline silicon over said dielectric layer;
• e) forming a patterned nonoxidizing layer over a first portion of said polycrystalline silicon such that said nonoxidizing layer overlies said first portion of said substrate and leaving a second portion of said polycrystalline silicon exposed;
• f) doping said second portion of said polycrystalline silicon with a first material having said first type conductivity;
• g) removing said nonoxidizing layer from said first portion of said polycrystalline silicon;
• and
• h) doping said first portion of said polycrystalline silicon with a second material having said second type conductivity,
• whereby said first portion of said polycrystalline silicon forms a first gate and said second portion of said polycrystalline silicon forms a second gate.

A process for doping a layer of polycrystalline silicon with a pair of dopant materials to form a pair of gates during the formation of a semiconductor device, said process comprising the following steps:

• a) doping a first portion of a semiconductor substrate with a first material having a first type conductivity;
• b) doping a second portion of said substrate with a second material having a second type conductivity;
• c) forming a layer of dielectric over said substrate;
• d) forming a layer of polycrystalline silicon over said dielectric layer;
• e) forming a patterned nonoxidizing layer over a first portion of said polycrystalline silicon such that said nonoxidizing layer overlies said first portion of said substrate and leaving a second portion of said polycrystalline silicon exposed;
• f) doping said second portion of said polycrystalline silicon to a first concentration with a first material having said first type conductivity;
• g) removing said nonoxidizing layer from said first portion of said polycrystalline silicon;
• and
• h) doping said first portion of said polycrystalline silicon to a second concentration with a second material having said second type conductivity, said second concentration being less than said first concentration such that said second portion of said polycrystalline silicon is lightly counterdoped with said second material, said second portion of said polycrystalline silicon substantially maintaining said first type conductivity thereby, said first and second portions of said polycrystalline silicon remaining substantially unoxidized at step h),
• whereby said first portion of said polycrystalline silicon forms a first gate and said second portion of said polycrystalline silicon forms a second gate.