Dynamic-type semiconductor memory device having staggered activation of column groups

An address multiplexing semiconductor memory device, comprising;

• a cell array including a plurality of memory cells arranged in rows and columns;
• row selection means responsive to a first address signal for selecting a corresponding row in said cell array, said first address signal being applied to said memory device at a first timing;
• buffer means responsive to a second address signal for generating a column group designating signal and applying said column group designating signal to column selection means, said first and second address being simultaneously applied to said semiconductor memory device;
• sense amplifier means provided for each respective column of said cell array for sensing and amplifying a signal potential on an associated column;
• activation means responsive to said column group designating signal for activating said sense amplifier means,
• column selection means responsive to said second address signal and a third address signal for selecting a corresponding column in said cell array, said third address signal being applied at a second timing different from said first timing.

In a method of operating a semiconductor memory device comprising a cell array having a plurality of memory cells arranged in a matrix of rows and columns wherein said columns are grouped into a first group of columns and a second group of columns, first sense amplifiers provided for the columns of said first group for sensing and amplifying signal potentials on associated columns and second sense amplifiers provided for the column of said second group for sensing and amplifying signal potentials on associated columns, including row selection means and column selection means a method of driving the sense amplifiers comprising the steps of:

• applying first and second address signals simultaneously to said semiconductor memory device;
• generating a column group designating signal, in response to said second address signal;
• applying said column group designating signal to said column selection means;
• activating, in response to said column group designating signal, said first sense amplifiers and said second sense amplifiers at different timings;
• wherein sense amplifiers provided for the columns corresponding to a column group designated by said column group designating are first activated,
• said row selection means are responsive to said first address signal applied to said semiconductor memory device to designate a row in said cell array at a first timing, and
• said second address signal constitutes a column address signal for designating a column in said cell array when combined with a third address signal applied at a second timing different from said first timing.

In a method of operating a semiconductor memory device including a cell array having a plurality of memory cells arranged in a matrix of rows and columns wherein said columns comprise a first group of bit line pairs each having at least one crossing portion therein and a second group of bit line pairs each having no crossing therein, first sense amplifiers provided for the bit line pairs of said first group for sensing and amplifying signal potentials on associated bit line pairs, and second sense amplifier provided for the columns of said second group for sensing and amplifying signal potentials on associated bit line pairs, and wherein said bit line pairs of said first group and bit line pairs of said second group are arranged alternately in said cell array including row selection means and column selection means, a method of driving the sense amplifiers comprising the steps of:

• applying first and second address signals simultaneously to said semiconductor memory device;
• generating a column group designating signal, in response to said second address signal,
• applying said column group designating signal to said column selection means;
• activating, in response to said group designating signal, said first sense amplifiers and said second sense amplifier at different timings;
• wherein sense amplifiers corresponding to a column group provided for the bit line pairs designated by said group designating signal are first activated,
• said row selection means are responsive to said first address signal applied to said semiconductor memory device at a first timing to designate a row in said cell array, and
• said second address signal constitutes a column address signal for designating a column in said cell array when combined with a third address signal applied thereto at a second timing different from said first timing.

A method for operating a semiconductor memory device comprising a cell array including a plurality of memory cells arranged in rows and columns including column selection means, comprising the steps of:

• receiving a first address signal for generating a row designating signal for designating a row in said cell array;
• receiving a second address signal simultaneously with said first address signal;
• generating a column group designating signal in response to said second address signal;
• applying said column group designating signal to said column selection means;
• receiving a third address signal at a timing different from that of said first and second address signals to combine said third address signal with said second address signal to generate a column designating signal designating a column in said cell array;
• and
• activating sense amplifiers in a column group designated by said column group designating signal before activating sense amplifiers in column groups not designated by said column group designating signal.